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Re: Discussion about a new development plan? (was: Re: [tree-ssa] AST optimizer in C++?)

> (most of you already know this, so skip it or correct me)
> Right now there are at least four projects ongoing that involve lots of
> infrastructure changes or major rewrites:
> 1) The new (tree-based?) optimizer framework that people are working
>    on in the tree-ssa branch.
> 2) The other "major rework" project on the cfg-branch, where Jan Hubicka
>    and others were working on loop optimizers and midRTL.

Concerning cfg-branch, I plan to create (in fact I've already did) a new branch
called rtlopt-branch, where RTL based optimizes in the shape ready for GCC
merging (ie not breaking many architectures and provably improving code
quality) should go.  I plan to move there the optimizes from cfg-branch so we
won't slip release schedule again as happent previously and plan to move
forward in the direction of removing loop and cse optimizers and replacing them
with something sane.

I didn't included any code to rtlopt branch nor announced it yet, as I would
like to get daily benchmarking of it working first and the machine doing so
have problems, Andreas is working on it.

I also plan to create midrtl-branch in near future and place there the work for
midrtl I done so far.  In the first stage I would target for code mergeable
into mainline in near future that just cleans up the insn-* interface and
virtualises it, so multiple machine descriptions can be compiled into compiler
(it works for me already to some extend - like that insn-attrtab and firends
are not virtualised as it is not needed for the midrtl project)

Then i would like to move in the direction to midrtl, once the ast matures
enought so we can cleanup the RTL generation enought to make this possible.


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