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Re: Bytes order and words order
- From: Gabriel Dos Reis <gdr at integrable-solutions dot net>
- To: Matt Austern <austern at apple dot com>
- Cc: Richard dot Earnshaw at arm dot com, gcc at gcc dot gnu dot org
- Date: 23 Aug 2002 22:32:39 +0200
- Subject: Re: Bytes order and words order
- Organization: CodeSourcery, LLC
- References: <A997805C-B6CF-11D6-94D6-00039390D9E0@apple.com>
Matt Austern <email@example.com> writes:
| On Friday, August 23, 2002, at 12:13 PM, Gabriel Dos Reis wrote:
| > | On the PPC a qNaN
| > | has the most significant fraction bit 1 and an sNaN has 0,
| > Yes, that is what I have on SPARCs too.
| > | and
| > | for MIPS it's the other way around.
| See table B-2 in the MIPS IV Instruction Set reference,
| which you can find at this rather inconvenient URL:
Thanks a lot. Indeed, that complicates a little bit the task. I'll
have to go back and double-check the IEEE-754 (which I don't have handy
It is interesting to note that real.[ch] just treats them equally
without distinguishing a QNaN from an SNaN.