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RE: generation of divxu opcode for H8300
- From: "Dhananjay R. Deshpande" <dhananjayd at kpit dot com>
- To: "Andrew Haley" <aph at cambridge dot redhat dot com>
- Cc: "Sanjiv Kumar Gupta, Noida" <sanjivg at noida dot hcltech dot com>,<gnuh8 at gnuh8 dot org dot uk>,<gcc at gcc dot gnu dot org>
- Date: Mon, 8 Jul 2002 10:04:11 +0530
- Subject: RE: generation of divxu opcode for H8300
Hi
>
> > The divxu instruction divides the contents of a 16-bit register Rd
> > (destination register) by the contents of an 8-bit register Rs
> > (source register) and stores the result in the 16-bit register
> > Rd. The division is unsigned. The operation performed is 16 bits
> > ÷ 8 bits -> 8-bit quotient and 8-bit remainder. The quotient is
> > placed in the lower 8 bits of Rd. The remainder is placed in the
> > upper 8 bits of Rd. Valid results are not assured if division by
> > zero is attempted or an overflow occurs.
>
> "Valid results are not assured." Nasty.
>
> > So this instruction cannot be directly used for 16-bit/8-bit
> > division. For e.g. if you are dividing 0xFFF0 by 2, then quotient
> > is 0x7FF8 which can't be stored in 8 bits, so overflow occurs. So
> > divxu.b can only be used for 8-bit/8-bit division.
>
> Right, but that in no way explains why divxu.b is only disabled on
> H8300.
Yes, divxu.b should be generated for 8-bit/8-bit division on H8300. In
message http://gcc.gnu.org/ml/gcc/2002-07/msg00200.html it is mentioned that he will enable generation of divxu.b for H8300.
Regards,
Dhananjay
>
> Andrew.
>