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RE: generation of divxu opcode
- From: "Dhananjay R. Deshpande" <dhananjayd at kpit dot com>
- To: "Sanjiv Kumar Gupta, Noida" <sanjivg at noida dot hcltech dot com>,<gnuh8 at gnuh8 dot org dot uk>
- Cc: <gcc at gcc dot gnu dot org>
- Date: Fri, 5 Jul 2002 17:48:19 +0530
- Subject: RE: generation of divxu opcode
Hi,
> -----Original Message-----
> From: Sanjiv Kumar Gupta, Noida [mailto:sanjivg@noida.hcltech.com]
> Sent: Tuesday, July 02, 2002 5:14 PM
> To: gnuh8@gnuh8.org.uk
> Subject: generation of divxu opcode
>
>
> Hi,
>
> I wonder why h8300-hms-gcc does not generate "divxu" opcode.
> it rather uses
> a function call even for 16-bit/8-bit division. Any idea why
> such behaviour.
>From the H8300 programming manual -
The divxu instruction divides the contents of a 16-bit register Rd (destination register) by the contents of an 8-bit register Rs (source register) and stores the result in the 16-bit register Rd. The division is unsigned. The operation performed is 16 bits ÷ 8 bits -> 8-bit quotient and 8-bit remainder. The quotient is placed in the lower 8 bits of Rd. The remainder is placed in the upper 8 bits of Rd. Valid results are not assured if division by zero is attempted or an overflow occurs.
So this instruction cannot be directly used for 16-bit/8-bit division. For e.g. if you are dividing 0xFFF0 by 2, then quotient is 0x7FF8 which can't be stored in 8 bits, so overflow occurs. So divxu.b can only be used for 8-bit/8-bit division.
On H8300/H and H8/S there is divxu.w instruction which performs 32-bit/16-bit division. To perform 16-bit/8-bit division the compiler extends these to 32 bit and 16 bit respectively and use divxu.w instruction.
Regards,
Dhananjay
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
> Thanks and Regards
> Sanjiv
>
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