Re: The perennial i386 floating-point rounding issue...

[Ross Smith <r-smith at ihug dot co dot nz>]

On Thursday, 13 June 2002 06:41, Jan Hubicka wrote:
> > >-march isn't a reliable guide to whether SSE is available, at
> > > least for AMD chips. According to AMD's docs, everything from the
> > > Athlon 4 (a.k.a. Thunderbird) on has been made in both SSE and
> > > no-SSE versions, and the only reliable way to detect SSE is via
> > > the feature flags from the CPUID instruction.
> >
> > Sorry, this just isn't true.  No Thunderbirds (aka Athlon model 4)
> > were ever made with SSE support.
>
> Thats it.  THere is little bug in SPECs making GCC to define __SSE__
> for tbirds.  I believe it is fixed already, I will double check.

It's present in the 3.1 release. (That wasn't what I was going by, 
though; see below.)

> > Perhaps you are confusing the "Mobile AMD Athlon??? 4" which is the
> > name of their mobile processor based on the Palomino core aka
> > (Athlon model 6).  All the processors based on this core (or the
> > newest model 8 core) are SSE capable.

(I think you mean model 7 (Thoroughbred), which is what the current 
top-of-the-line Athlons are based on. Presumably Barton will be model 
8, and Clawhammer model 9.)

I wasn't aware of the Mobile Athlon mess, but on checking AMD's site, 
you're right; "Mobile Athlon 4" is actually a model 6.

#insert <std_marketroid_flame>

The phrase "first against the wall when the revolution comes" wanders 
across my mind...

I was going by the information in AMD's document on the CPUID 
instruction:
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/20734.pdf
(I don't know if Kmail will wrap that URL)

Quoting from it (page 12):

> If bit 25 of the standard feature flags is set to  1  on an AMD
> Athlon or AMD Duron model 6 or greater, SSE instructions are
> supported. Optionally, if bit 25 of the standard feature flags
> is set on any previous AMD processor, it has streaming SIMD
> extensions (SSE) capabilities.

This clearly implies that some pre-model-6 chips (i.e. model 4 
(Thunderbird); model 5 (Mustang) was never put into production) had SSE 
capability, and that some model-6+ chips don't. The latter is supported 
by the list later in the document showing the feature flag values for 
all AMD chips, which shows _all_ chips, up to and including model 7, as 
having the SSE bit _off_ by default.

I was also going by the behaviour of GCC in response to the -mathlon* 
options. SSE is enabled (internally, I mean, not going by the erroneous 
__SSE__ preprocessor macro) for -mathlon-4, -mathlon-mp, and 
-mathlon-xp, but not for -mathlon or -mathlon-tbird. I took that to 
mean that -mathlon-tbird was intended to mean "Athlon model 4 without 
SSE", while -mathlon-4 meant "Athlon model 4 with SSE". I didn't know 
about the Mobile Athlon quote-4-unquote mess; now that I do, I assume 
this is the chip -mathlon-4 was meant to refer to.

I think some of those options should be renamed, or at least carefully 
documented; surely it's natural to assume that -mathlon-4 means Athlon 
model 4? Most people aren't likely to know about the Mobile Athlon 
mess. (I'll volunteer to write some documentation for this area if 
necessary.)

Kelley, where did you get your information from? It took me some effort 
in cross-checking between the information on AMD's site and third-party 
sites (notably sandpile.org) to put together a definitive list of AMD 
chips and what was enabled (according to the docs) on each of them. If 
there's a more reliable source that I haven't found, I'd like to know 
about it.

CPU                aka           MMX       3DNow     SSE
K5                 --            no        no        no
K6                 --            yes       no        no
K6-II              --            yes       yes       no
K6-III             --            yes       yes       no
Athlon model 1     K7            extended  extended  no
Athlon model 2     K75           extended  extended  no
Duron model 3      Spitfire      extended  extended  no
Athlon model 4     Thunderbird   extended  extended  optional
Athlon XP model 6  Palomino      extended  extended  optional
Duron model 6      Morgan        extended  extended  optional
Athlon XP model 7  Thoroughbred  extended  extended  optional

-- 
Ross Smith ..................................... Auckland, New Zealand
r-smith@ihug.co.nz ...................................................

  "Never underestimate the power of stupid things in large numbers."
                                                      -- Serious Sam