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Re: gcc compile-time statistics

On Wed, May 22, 2002 at 12:47:47AM -0700, David S. Miller wrote:
>    From: Geoff Keating <>
>    Date: 18 May 2002 19:06:13 -0700
>    I looked at the reason for the slowdown, and it seems likely the
>    reason for the slowdown between 3.0.4 and 3.1 at -O0 on x86 is more
>    complex RTL.  Not more insns (in fact, fewer insns), but more
>    complexity within each insn.  Reload is taking twice as long to handle
>    fewer insns, ggc_alloc is called 30% more times, and so on.
> Note my other posting today wrt. N_REGISTER_CLASSES.
> On x86 from 3.0.x to 3.1 this went up from 19 to 25
> That does account for the increase in reload
> and regclass time.

What are e.g. FP_TOP_SSE_REGS and FP_SECOND_SSE_REGS classes good for?
Are they there just for completeness? There is no class for union of DREG
and SIREG either for example.
I see no .md pattern which would accept either %st (resp %st(1)) or an SSE
register and cannot imagine somebody would write such assembly.


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