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Re: Post-register-allocation opportunitistic optimizer?

From: Richard Henderson <rth at redhat dot com>
To: tm <tm at mail dot kloo dot net>
Cc: gcc at gcc dot gnu dot org, kazu at cs dot umass dot edu, joern dot rennecke at superh dot com
Date: Fri, 3 May 2002 17:05:58 -0700
Subject: Re: Post-register-allocation opportunitistic optimizer?
References: <20020503162220.A6106@redhat.com> <Pine.LNX.4.21.0205031617550.12511-100000@mail.kloo.net>

On Fri, May 03, 2002 at 04:46:03PM -0700, tm wrote:
> So we can naively emit long sequences of single shifts, and have peep2
> clean it up for us later if hard registers are available. Nice!

Um, except that peep2 only works with adjacent instructions.
You're probably better off modeling these as a single insn
through reload and splitting them with peep2.

r~

References:
- Re: Post-register-allocation opportunitistic optimizer?
  - From: Richard Henderson
- Re: Post-register-allocation opportunitistic optimizer?
  - From: tm

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