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Re: Post-register-allocation opportunitistic optimizer?
- From: law at redhat dot com
- To: Kazu Hirata <kazu at cs dot umass dot edu>
- Cc: tm at mail dot kloo dot net, gcc at gcc dot gnu dot org, joern dot rennecke at superh dot com
- Date: Fri, 03 May 2002 15:41:42 -0600
- Subject: Re: Post-register-allocation opportunitistic optimizer?
- Reply-to: law at redhat dot com
In message <20020503.172316.55515951.kazu@cs.umass.edu>, Kazu Hirata writes:
> Hi Toshi,
>
> > For example, GCC generates this code for a right shift by 8 on the
> > H8/300H:
> >
> > mov.w e0,r2
> > mov.b r0h,r0l
> > mov.b r2l,r0h
> > mov.b r2h,r2l
> > exts.w r2
> > mov.w r2,e0
>
> I was thinking about the same thing. Shifts that require loops are in
> the same situation. Also, if you want to use stw.l for argument push
> on H8/S, you need to know what registers are available, but this might
> require MACHINE_DEPENDENT_REORG.
>
> > 3. New optimizer pass which runs after global alloc which
> > opportunistically replaces slow sequences with fast sequences if hard
> > registers are available.
>
> This sounds very reasonable to me.
Look at how peephole2 works. It's designed to be able to replace one sequence
with another (possibly faster, smaller, whatever) when hard registers are
available.
jeff