This is the mail archive of the
gcc@gcc.gnu.org
mailing list for the GCC project.
Re: DFA for PPro, P2, P3
> In message <20020502170825.B5227@redhat.com>, Richard Henderson writes:
> > On Thu, May 02, 2002 at 04:55:46PM -0600, law@redhat.com wrote:
> > > (define_insn_reservation <latency>
> > > <attribute test to select the insn type for I2>
> > > "(p0|p1)+p0")
> >
> > Isn't that rather "(p0|p1),p0"? After all, the second uop
> > doesn't issue on the same cycle.
> That's one of the things that is (to me at least) extremely unclear about
> the PPro/P2/P3 pipeline -- ordering/dependency of uops.
>
> If you've got good documentation on this it's fairly trivial to change it;
> in fact, the ability to model that kind of information is one of the
> other key advantages of the DFA model.
The main problem is the scheduler stage in between of uops issue.
We can't model it properly and to my experience model attempting to model
the operations in right order and model issuing them all at once are
equivally bad, at least for Athlon.
Honza
>
> jeff