Re: paradoxical subreg problem [ patch attached ]

[kenner at vlsi1 dot ultra dot nyu dot edu (Richard Kenner)]

    We then simplify the zero_extension into a subreg, which is OK given
    #2 in the semantics Jim detailed.

I disagree and I think this is the core of the problem.  The ZERO_EXTEND
forces the high bits to zero, but the paradoxical subreg says we don't
know/care what they are.  I don't think that's a valid "simplification".

    Consider that we're comparing op0 and op1 for equality -- both operands
    are SImode, so we're doing a 32bit comparison.  Narrowing the operands
    to a smaller mode effectively removes bits from consideration.  

But that's fine since we should only have this when we don't *want* those
bits to be considered, which is not the case above.

    So it seems like there's three cases to consider.

No, I really don't think so.  I see no reason to get LOAD_EXTEND_OP
involved here.  I'd rather say it's identical to the register case.