force instruction

[Dmitry <diwil at mail dot ru>]

Fellows,

I define instruction:

(define_insn "sbrx_branch1248"
  [(set (pc)       
        (if_then_else
         (match_operator 0 "comparison_operator"
                         [(zero_extract
                           (match_operand:SI 1 "register_operand" "r")
                           (const_int 1)
                           (match_operand 2 "immediate_operand" "n"))
                          (const_int 0)])
         (label_ref (match_operand 3 "" ""))
         (pc)))]
  "(GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE)"
" 
	... proper coding ...
"
  [(set (attr "length")
        (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -510))
                           (le (minus (pc) (match_dup 3)) (const_int 513)))
                      (const_int 2)   
                      (const_int 4)))
   (set_attr "cc" "clobber")])

which should serve perfectly:
{
  volatile long a;
  long INTVALSOMETHING = (1<<18);
  while(a&INTVALSOMETHING) ;
}

But the compiler does not want to generate branch1248.
Instead it does something like

.L0:
	move a, reg			;	movsi:SI
	and INTVALSOMETHING, reg	;	andsi:SI
	test reg			;	tstsi:SI
	branchifnotzero .L0		;	bne

which is absolytelly correct, but much longer and expensive.

But when I define HI mode, gcc issuess brx_branch1248hi, but this hase no advantages
in comparison with 'multi-instructional' coding.

Did I miss something?

Host params:
sizeof long == 4;
sizeof int = 2;
units per word 2

If I write (define_insn "*sbrx_branch1248" 
				...
or set up modes of all operands (any reasonable combination) it does not help much.


Thanks,
Dmitry.


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