Re: powerpc & unaligned block moves with fp registers

[David Edelsohn <dje at watson dot ibm dot com>]

>>>>> DJ Delorie writes:

DJ> 1. Do we *ever* want to use fp regs for unaligned mem-mem moves?  Is
DJ> there any 32-bit PPC chip where an unaligned 64-bit fp move is
DJ> faster than two (maybe unaligned, maybe mot) 32-bit moves?

	What is your definition of "unaligned"?  Anything other than
natural alignment?

	PowerPC is good at word-aligned FP double-word moves.  Less than
word aligned is discouraged.  Is double-word aligned, better?  Yes.  But
PowerPC does not require strict alignment.

	Using more loads and stores of smaller units rapidly encounters
issues about performance hits from more instructions and I-cache usage.
Do not assume that multiple naturally aligned loads and stores is best.
For completely unaligned addresses, the choice between naturally aligned
loads/stores and the PowerPC load/store string instructions is even more
complicated. 

	I still have not heard a good justification why this approach is
addressing the cause and not the symptom.  GCC chose to use DImode and now
one is substituting SImode behind its back.  Just because the object is
DImode-sized and the PowerPC port allows DImode does not mean that GCC
should use DImode.  Undo-ing GCC's wrong choice after the fact seems like
we are solving the problem too late in the process.

	It seems that people are generating changes within the PowerPC
port simply because it is a place to hide these sort of kludges.  I don't
disagree with the goal.  I simply have not been convinced that the
appropriate location for the change has been found.

David