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Re: floor on i386

----- Original Message -----
From: "Jan Hubicka" <>
To: "Brad Lucier" <>
Cc: "Jan Hubicka" <>; "Alexandre Oliva"
<>; "Joe Buck" <jbuck@synopsys.COM>; "Chris
Lattner" <>; <>
Sent: Tuesday, September 25, 2001 8:00 AM
Subject: Re: floor on i386

> > > Major problem still remains in reload.
> > > If we don't want to get exact IEEE by setting proper
precisity before each
> > > mathematic operation (as SH4 does IMO), we will run into
problems with spills ,
> > > since these can be put in place control word is set to some
wrong value
> > > resutlting in wrong rounding before storing.
> >
> > If spills spilled the extended precision value, which is
> > anyway for proper IEEE conformance, this wouldn't be an
> Yes, but it is big performance problem when done, at least for
AMD CPUs, where
> XFmode spills cost a lot more than DF/or SFmode, so it should
not be enabled unconditionally.
> (I was trying to implement this idea in the past and it appears
to be quite dificult to do
> too :( )
> Honza
> >
> > Brad

XFmode spills should not be so expensive if 16-byte alignment
could be assured.  Those people who set the CPU into 53-bit
precision mode, as well as those who don't like the alignment
requirement, would want a way to keep the current scheme.

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