mul + div with 64 bit signed ints on IA32

[Frank Klemm <pfk at fuchs dot offl dot uni-jena dot de>]

There are possibilities to speed up the following operations for IA32

	int64_t * int64_t

	int64_t / int64_t

	int64_t % int64_t	(?)

Interests? Is this used in any benchmark?


Another floating point problem are the rounding bits of the FPU.
It should be forced that these two bits are always '11' (round to zero).
This would decrease code size and speed up significantly the code.

I know the is a problem with ill written assembler code which polutes these
two bits. May be a compiler switch switches between 'safe' and 'fast'
behaviour. If you have 'clean' assembler libs, you can use 'fast', otherwise
you must use 'safe'.

It is stupid to save, modofy and restore the RC bits several million times
per second, especially because this operation is VERY expensive.

A rounding of a 'double' to an 'int' with ANSI-C took 160 clocks on a K6-2.
In the same time it was possible to calculate the scalar of _two_ 1200 byte
long vectors of float values. This is brain dead!

Here we have problems with the design of C and with the design of the FPU
of the iA32 architecture.


Option proposals:

	-fsaverc
	-ffastrc
	-fsavecld	; the same for the cld flag
	-ffastcld

-- 
Frank Klemm