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Re: [RFC] patch: Re: reg+reg addressing mode on SPARC

To: Dan Nicolaescu <dann at godzilla dot ICS dot UCI dot EDU>
Subject: Re: [RFC] patch: Re: reg+reg addressing mode on SPARC
From: Jakub Jelinek <jakub at redhat dot com>
Date: Mon, 13 Aug 2001 13:04:06 -0400
Cc: Joe Buck <jbuck at synopsys dot com>, gcc at gcc dot gnu dot org
References: <200108110107.SAA09804@atrus.synopsys.com> <200108101846.aa22556@gremlin-relay.ics.uci.edu> <20010811080319.A510@sunsite.ms.mff.cuni.cz> <200108130951.aa18893@gremlin-relay.ics.uci.edu>
Reply-To: Jakub Jelinek <jakub at redhat dot com>

On Mon, Aug 13, 2001 at 09:51:34AM -0700, Dan Nicolaescu wrote:
> Are you sure? (I have no idea...)
> Is anything taking into account that reg+reg is using 2 registers,
> thus increases the register pressure? 

By setting ADDRESS_COST to 2 for reg+reg and 1 otherwise you say that
add %reg1, %reg2, %reg3
ld [%reg3], %reg4
is as fast as
ld [%reg1 + %reg2], %reg4
which is not true. All addressing modes are expensive equally on all chips
I know of.

	Jakub

References:
- Re: reg+reg addressing mode on SPARC
  - From: Joe Buck
- [RFC] patch: Re: reg+reg addressing mode on SPARC
  - From: Dan Nicolaescu
- Re: [RFC] patch: Re: reg+reg addressing mode on SPARC
  - From: Jakub Jelinek
- Re: [RFC] patch: Re: reg+reg addressing mode on SPARC
  - From: Dan Nicolaescu

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