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Re: Number of registers on x86
- To: dewar at gnat dot com
- Subject: Re: Number of registers on x86
- From: Toshi Morita <tm2 at best dot com>
- Date: Mon, 29 Jan 2001 23:45:13 -0800 (PST)
- Cc: gcc at gcc dot gnu dot org
> <<Right. There is little research in the area, except to say that hardware
> register renaming isn't anywhere near as efficient as doing it in the
> compiler (I noticed this just scanning web pages).
> It was just a thought.
> Are you sure this is general wisdom. I thought the ia64 design still
> had hardware renaming despite having loads of registers.
IIRC, IA64 is the architecture description for a class of procesors rather
than the description of a single implementation.
Therefore, it is probably semantically incorrect to discuss whether the
IA64 has hardware register renaming or not.
Merced is known not to out-of-order execution capability nor have hardware
register renaming. They've eschewed it in favor of compiler scheduling and
"software register renaming" implemented in the form of rotating registers.
> Of course the time that hardware register renanming is useful is when
> there are very few hardware registers (the techniques were I think first
> exploited extensively by IBM dealing with only four floating-point
> registers on the mainframe architecture).
> After all having a small number of hardware registers means shorter
> instructions, which means lower pressure on the icache. These are all
> delicately balanced tradeoffs.
> In any case, this claim can be left moot, since the issue is doing a good
> job on the ia32, which does make extensive use of renaming. It is not really
> relevant to say that the ia32 should have more hardware registers :-)
The IA32 likewise also encompasses a class of processors rather than a
single implementation, so I believe this is an inaccurate statement.
The 8086, 80186, 80286, 80386, 80486, and Pentium all are in-order execution
processors, so therefore they do not use register renaming at all.
The Pentium Pro and its derivatives (P2 and P3) and also the P4 have
out-of-order execution capability and use hardware register renaming.