Status of vector-extension infrastructure

["Thomas Womack" <tom at womack dot net>]

I have read in several places that gcc-3.0 will have SSE1 support, but I
haven't been able to find any more information about this than the single
assertion. Is there an obvious place to look which I've not found yet?

There are enough machine architectures with some sort of vector support
around that I'm assuming gcc will have some sort of extension meaning that I
could compile the same source code on P3 and Altivec and get the same
results (and reasonable speed provided that I stuck to the subset of
commands that both chips support); am I being too utopian about this?

_simd_char_sum_of_absolute_differences(), for example, is accelerated on
most current-generation hardware, at least for _simd_char_8 datatypes.

I could imagine

_simd_char_16 A,B;
C = _simd_char_saturating_signed_add(A,B);

has the potential to produce better code even on architectures without
PADDUSB xmm0,xmm1 [Altivec and P4] than

for (int i=0;i<16;i++) {int j=A[i]+B[i];j=(j<0?0:j);j=(j>255?0:j);C[i]=j;}

simply by outputting a chunk of well-scheduled prefabricated inline
assembler to do the operation [on a 32-bit architecture you could do at
least two at a time by masking 0xff00ff00 and 0x00ff00ff to get space for
carries ...]

There are, of course, alignment issues.

If I'm being *really* utopian, I'd like to be able to do

_simd_float_1048576 *U,*V,*W;
*U+=(*V + 2*(*W));

and have it generate scheduled cache-blocked vector-accelerated code on
whatever architecture I use, but that's an *enormous* language extension. I
can't quite see how to get there in any other way.

Tom