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RE: Note handling in haifa-sched.


FYI: S means size information (i.e. 1 byte), C cycles, T instruction type
(there are some grouping restrictions on the machine I am working on) and U
execution unit.
There are 2 AAU execution units on the processor in question.

As you can easily see, insns 47 and 45 depend on insn 44 (true dependence).
Also,
because there are only two AAU units, they CANNOT execute simultaneously,
under no conditions. Though, if I am to consider what you said as true( " We
already set the mode of the insn beginning a new cycle. ") I would consider
these three instructions in the same execution set - and this is wrong.
Note: Haifa's visualization mechanism works fine - it groups together 47 and
45, after
executing 44.

;; DLB info: (S 1) (C 1) (T 4) (U AAU)
(insn:TI 44 40 47 (set (reg:QI 18 r2)
        (mem:QI (post_inc:SI (reg:SI 17 r1)) 0)) 151 {movhi-1} (insn_list 40
(insn_list 40 (nil)))
    (expr_list:REG_INC (reg:SI 17 r1)
        (nil)))

;; DLB info: (S 1) (C 1) (T 1) (U AAU)
(insn 47 44 45 (set (mem/s:SI (reg:SI 16 r0) 0)
        (reg:SI 17 r1)) 156 {movsi+1} (insn_list 38 (insn_list 40 (insn_list
44 (insn_list 46 (nil)))))
    (expr_list:REG_DEAD (reg:SI 17 r1)
        (expr_list:REG_DEAD (reg:SI 16 r0)
            (nil))))

;; DLB info: (S 1) (C 1) (T 2) (U AAU)
(insn 45 47 173 (set (reg/v:SI 23 r7)
        (zero_extend:SI (reg:QI 18 r2))) 161 {zero_extendqisi2} (insn_list
44 (insn_list 44 (nil)))
    (expr_list:REG_DEAD (reg:QI 18 r2)
        (nil)))

   Another thing: no jump_insn has the TImode set (and obviously the jump
cannot be groupped with the test before it). Still, this might be treaded as
a 'special case'. But the above can't.
   So I guess your suggestion was wrong.

Virgil


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