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Re: RFC: Prefetch instruction support
- To: Jan Hubicka <hubicka at atrey dot karlin dot mff dot cuni dot cz>
- Subject: Re: RFC: Prefetch instruction support
- From: Michael Meissner <meissner at cygnus dot com>
- Date: Tue, 11 Apr 2000 19:08:53 -0400
- Cc: egcs at egcs dot cygnus dot com, alex dot dreyzen at amd dot com, norbert dot juffa at amd dot com
- References: <20000411164306.B12560@atrey.karlin.mff.cuni.cz>
On Tue, Apr 11, 2000 at 04:43:06PM +0200, Jan Hubicka wrote:
>
> Hi
> During last weekend I've implemented basic prefetch instruction framework
> (tested on Athlon) based on the suggestions of Alex Dreyzen and Norbert Juffa
> from AMD.
>
> Basically it examines loops for arrays traversed and generate prefetches few
> cache lines forward. Also it is able to suggest unroll_number for loop unroller
> to fetch one cache line per loop iteration (in order to avoid
> prefetching of single page multiple times). This results in massive loop
> unrolling (up to 64 times on Athlon), but seems to do good job. Later we may
> want to tweak this heruistics.
>
> Here are few implementation details:
>
> The prefetch instruction is represented as:
>
> (insn 92 28 30 (unspec_volatile[
> (plus:SI (plus:SI (mult:SI (reg/v:SI 26)
> (const_int 4 [0x4]))
> (reg:SI 29))
> (const_int 128 [0x80]))
> ] 1) -1 (nil)
> (nil))
I would prefer new RTL codes to represent the prefetch:
(insn 92 28 30 (prefetch (mem:SI (plus:SI (plus:SI (mult:SI (reg/v:SI 26)
(const_int 4))
(reg:SI 29))
(const_int 128)))))
--
Michael Meissner, Cygnus Solutions, a Red Hat company.
PMB 198, 174 Littleton Road #3, Westford, Massachusetts 01886, USA
Work: meissner@redhat.com phone: +1 978-486-9304
Non-work: meissner@spectacle-pond.org fax: +1 978-692-4482