Need advice on interface to non-gcc scheduler

[Steven Roos <S dot Roos at its dot tudelft dot nl>]

Hi,

Currently I am working on an instruction scheduler for a new computer
architecture. This new architecture is not like any current
architecture and I guess there is no way to make gcc generate code
for it. 

The architecture looks like an extremely wide VLIW with limited
connectivity. To avoid long wires wherever possible, all resources
are distributed over all units. The concept of a centralized register
file does not exist. When scheduling an instruction all related data
transports have to be scheduled explicitly too.

My idea is to use as much of gcc as possible and send the gcc RTL code
to a dedicated scheduler just before gcc would do its own scheduling.

I would like some advice on how to implement this interface. How hard is 
it to generate such an interface? Can I get all sorts of analysis info 
(mem alias, data flow, control flow) through this interface? How about 
profiling info and debug info?

Greetings,
Steven Roos
Delft University of Technology