Re: Floating-point Consistency, -ffloat-store, and x86 (mostly)

[N8TM at aol dot com]

In a message dated 12/14/98 11:57:20 PM Pacific Standard Time, burley@gnu.org
writes:

<< Either the FPU must be switched back and forth
 among the two modes (32 and 64), which is, apparently, dog slow
 on current chips, or we get right back into the double-rounding
 and exponent-range problems, >>

There isn't a double rounding problem with doing single precision in the
double precision rounding mode, at least not for single addition, subtraction,
and multiplication operations, as there is no round-off  when a double
precision result is obtained from a single precision operation. 

<< switching to 80-bit spills seems least likely
to hurt anyone, to noticably hurt performance >>

Switching from 32-bit spills to improperly aligned 80-bit spills will bring a
noticeable reduction in performance.  Lahey just admitted the error of their
ways in their mis-aligning of COMMON blocks in the compiler versions of recent
months. Some of the Livermore Kernels suddenly took as much as 6 times as long
to run, due to mis-alignments, but today's lf90 version is back to being
generally faster than g77. Intel specifically recommend 128-bit aligned
storage for 80-bit quantities.