combine_givs_p address cost

[Michael Hayes <m dot hayes at elec dot canterbury dot ac dot nz>]

The following loop.c patch of Fri Jul 17 14:18:14 1998 to ignore the
address cost in combine_givs_p pessimises code for the C4x and
probably other machines that have autoincrement addressing modes.

      /* ??? Looses, especially with -fforce-addr, where *g2->location
	 will always be a register, and so anything more complicated
	 gets discarded.  */
#if 0
#ifdef ADDRESS_COST
      && ADDRESS_COST (tem) <= ADDRESS_COST (*g2->location)
#else
      && rtx_cost (tem, MEM) <= rtx_cost (*g2->location, MEM)
#endif
#endif

For example, the following function:

int ccopy1(const __complex__ float *a, __complex__ float *b, int size)
{
    int i;
    
    for (i = 0; i < size; i++)
	b[i] = a[i];
    return 1;
}

with the patch generates in the loop body from .loop:

(note 16 104 22 "" NOTE_INSN_LOOP_BEG)

(code_label 22 16 32 5 "")

(insn 32 22 34 (clobber (mem/s:QC (reg:QI 50) 0)) -1 (nil)
    (nil))

(insn 34 32 101 (set (reg:QF 45)
        (mem/s:QF (reg:QI 54) 0)) -1 (nil)
    (nil))

(insn 101 34 35 (parallel[ 
            (set (reg:QI 54)
                (plus:QI (reg:QI 54)
                    (const_int 2)))
            (clobber (reg:CC_NOOV 21 st))
        ] ) -1 (nil)
    (nil))

(insn 35 101 95 (set (mem/s:QF (reg:QI 53) 0)
        (reg:QF 45)) -1 (nil)
    (nil))

(insn 95 35 37 (parallel[ 
            (set (reg:QI 53)
                (plus:QI (reg:QI 53)
                    (const_int 2)))
            (clobber (reg:CC_NOOV 21 st))
        ] ) -1 (nil)
    (nil))

(insn 37 95 38 (set (reg:QF 46)
        (mem/s:QF (plus:QI (reg:QI 49)
                (const_int 1)) 0)) -1 (nil)
    (nil))

(insn 38 37 40 (set (mem/s:QF (plus:QI (reg:QI 50)
                (const_int 1)) 0)
        (reg:QF 46)) -1 (nil)
    (nil))

(note 40 38 71 "" NOTE_INSN_LOOP_CONT)


and without the patch:

(note 16 82 22 "" NOTE_INSN_LOOP_BEG)

(code_label 22 16 32 5 "")

(insn 32 22 34 (clobber (mem/s:QC (reg:QI 49) 0)) -1 (nil)
    (nil))

(insn 34 32 35 (set (reg:QF 45)
        (mem/s:QF (reg:QI 50) 0)) -1 (nil)
    (nil))

(insn 35 34 37 (set (mem/s:QF (reg:QI 49) 0)
        (reg:QF 45)) -1 (nil)
    (nil))

(insn 37 35 38 (set (reg:QF 46)
        (mem/s:QF (plus:QI (reg:QI 50)
                (const_int 1)) 0)) -1 (nil)
    (nil))

(insn 38 37 40 (set (mem/s:QF (plus:QI (reg:QI 49)
                (const_int 1)) 0)
        (reg:QF 46)) -1 (nil)
    (nil))

(note 40 38 71 "" NOTE_INSN_LOOP_CONT)


The latter generates muvh tighter code where the memory references
can all be turned into autoincrements.  It looks like we need some
sort of compromise to control this patch.


Michael.