This is the mail archive of the
gcc@gcc.gnu.org
mailing list for the GCC project.
Re: How to clean up i386 machine description?
- To: amylaar at cygnus dot co dot uk (Joern Rennecke)
- Subject: Re: How to clean up i386 machine description?
- From: Colin Douglas Howell <howell at cs dot stanford dot edu>
- Date: Thu, 12 Nov 1998 13:44:06 -0800 (PST)
- Cc: rth at cygnus dot com, hubicka at horac dot ta dot jcu dot cz, howell at cs dot stanford dot edu, law at cygnus dot com, pcg at goof dot com, egcs at cygnus dot com
Joern Rennecke writes:
>
> > Special patterns for inc/dec is ok, but which_alternative cannot
> > handle implementation specific instruction selection.
>
> special patterns for inc/dec are actually a problem; they should not be
> enabled before reload.
May I ask why not? I'm not yet familiar with the details of reload.
> If you need to order instruction alternatives differently for different
> CPUs or use different constraint modifiers so that the alternative
> selection is changed, currently the only way is to have different
> patterns for the different CPUs.
> I'm afraid this doesn't sound like much of a cleanup...
I don't think the goal is to have a clean-looking machine description;
the x86 architecture is itself too messy for that. The goal is to
have a description of the different x86 implementations which is
accurate enough to schedule them well. At the same time it should be
reasonable to maintain and should keep duplicated code and other
repetitions to a minimum.
> > > Also in some cases using attrubutes should be impossible. For example
> > > in many cases the non-prefix opcode is emited when cc0_probably_useless
> > > function is true. This decision is cotext depenedent.
> >
> > There must be another way to solve this. I will have to think
> > on this further.
>
> The cc0_probably_useless hack is probably useless. It violates the
> assumtions of gcc about targets that use cc0.
> I think you have to re-write the i386 target to explicitly use
> condition code registers (AFAIK there are actually separate integer
> and fp condition code registers?). These should probably be fixed
> registers.
Yes, the x86 floating-point condition code register is separate from
the integer one. What makes things really annoying is that you can't
use the floating-point condition codes directly for conditional
branches and sets. Instead you have to use the "fnsts" instruction to
transfer the floating-point condition codes to the %eax integer
register, and then either test %eax directly or use the "sahf"
instruction to set the integer condition codes from %eax. Only then
can you do a conditional branch or set.
In the current machine description this stuff is handled by the
function output_fp_cc0_set() in i386.c.
--
Colin Douglas Howell Systems Administrator
e-mail: howell@cs.stanford.edu Computer Facilities Group
office: (650) 723-2491 Computer Science Department
Stanford University