LIW optimisation pass

[Michael Hayes <michaelh at ongaonga dot chch dot cri dot nz>]

Is anyone working on targeting GCC to processors that have a long
instruction word (LIW) architecture or does anyone have a list of such
processors?

The C4x DSP I have been targetting has a limited LIW capability; it
has some instructions that can perform two distinct operations, such
as a multiply and an add, in parallel.

To utilise these dual pack instructions, I have written an
optimisation pass for GCC that follows after combine.  This looks for
dependent insns related by flow that can be packed into a parallel
insn.  If a pair of insns are found that can be packed together, a
copy of each insn in the loop is either hoisted or sunk from the loop
and the loop count is decremented.  Note that the optimisation is only
applied to simple unjumped loops where the iteration count can be
modified.


For example, a dot-product operation, (where REPEAT denotes a pseudo RTL
op for a zero overhead loop construct):

(repeat (code_label loop) (reg 4))
(set (reg 0) (mult (mem (post_inc (reg 1))) (mem (post_inc (reg 2)))))
(set (reg 3) (plus (reg 3) (reg 0)))
(code_label loop)

is converted into the following (ignoring for clarity the bypass jump
that is required if the iteration count in reg 4 becomes negative):

(set (reg 4) (plus (reg 4) (const_int -1)))
(set (reg 0) (mult (mem (post_inc (reg 1))) (mem (post_inc (reg 2)))))
(repeat (code_label loop) (reg 4))
(parallel [ (set (reg 0) 
                 (mult (mem (post_inc (reg 1))) (mem (post_inc (reg 2)))))
            (set (reg 3) 
                 (plus (reg 3) (reg 0))) ])
(code_label loop)
(set (reg 3) (plus (reg 3) (reg 0)))

Note that the first multiplication is hoisted out of the loop since
the result (in reg 0) is required for the addition.  The addition insn
is sunk from the loop for the last iteration.

Currently, the optimisation is part of the C4x backend since I look
for zero overhead loops that the C4x uses where I know that the
iteration count is in a register.  Any comments or ideas to make the
optimisation more generic would be appreciated.


Michael.