This is the mail archive of the
gcc@gcc.gnu.org
mailing list for the GCC project.
Re: Feature request: ability to describe x86 register halves as contraints.
- To: Joern Rennecke <amylaar at cygnus dot co dot uk>
- Subject: Re: Feature request: ability to describe x86 register halves as contraints.
- From: Bill Currie <bcurrie at tssc dot co dot nz>
- Date: Fri, 03 Jul 1998 09:33:03 +1200
- CC: law at cygnus dot com, ak at muc dot de, egcs at cygnus dot com
- Organization: Telecommunication Systems Support Centre
- References: <199807021720.SAA07510@phal.cygnus.co.uk>
Joern Rennecke wrote:
>
> Why don't you just re-number the registers so that their endianness matches
> that of memory?
I'd thought of that, but the problem is the floating point regs. This
would work nicely for the integer registers, but the i860 groups the fp
regs into pairs for DI mode regs:
MSW LSW
%f1 %f0
%f3 %f2
...
%f31 %f30
And the pairs must always be referred to by the lower regiters (%f0, %f2
... %f30).
Bill
--
Leave others their otherness