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Re: Suggested IRIX6 patch
- To: egcs at cygnus dot com
- Subject: Re: Suggested IRIX6 patch
- From: jerry at cs dot ucsb dot edu (Jeremiah W. James)
- Date: 26 Mar 1998 09:36:48 -0800
- References: <tpremzqo8op.fsf@cs.ucsb.edu>
- Reply-To: jerry at cs dot ucsb dot edu (Jerry James)
And, naturally, after posting that patch I found there was a typo in
it. Two typos, in fact. I left out two critical % characters in the
link spec. Here's the corrected patch. And I checked the rest of it
for typos, too. Really.
Thu Mar 26 09:37:15 PST 1998 Jerry James (jerry@cs.ucsb.edu)
* gcc/config/mips/iris6.h: Pass appropriate ABI and instruction set
options to the linker when the user doesn't set both.
* gcc/config/mips/mips.c (override_options): default to MIPS III
instead of MIPS IV when -mabi=64
* gcc/config/mips/mips.h: Pass appropriate ABI and instruction set
options to the assembler and cc1 when the user doesn't set both.
* gcc/invoke.texi: Add documentation for new MIPS ABI and instruction
set options. Add ABI defaults to description of -mips options.
diff -u gcc/config/mips/iris6.h.ORIG gcc/config/mips/iris6.h
--- gcc/config/mips/iris6.h.ORIG Fri Jan 2 15:38:15 1998
+++ gcc/config/mips/iris6.h Thu Mar 26 09:36:47 1998
@@ -531,11 +531,11 @@
%{!mabi*:%{mips4:/usr/lib32/mips4/crtn.o%s}\
%{!mips4:/usr/lib32/mips3/crtn.o%s}}}"
-/* ??? If no mabi=X option give, but a mipsX option is, then should depend
- on the mipsX option. */
#undef LINK_SPEC
#define LINK_SPEC "\
-%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
+%{G*} %{EB} %{EL} \
+%{mips1:%{!mabi*:-32} -mips1} %{mips2:%{!mabi*:-32} -mips2} \
+%{mips3:%{!mabi*:-n32} -mips3} %{mips4:%{!mabi*:-64} -mips4} \
%{bestGnum} %{shared} %{non_shared} \
%{call_shared} %{no_archive} %{exact_version} %{w} \
%{static: -non_shared} \
@@ -543,4 +543,4 @@
%{!shared: %{!non_shared: %{!call_shared: -call_shared -no_unresolved}}}} \
%{rpath} -init __do_global_ctors -fini __do_global_dtors \
%{shared:-hidden_symbol __do_global_ctors,__do_global_dtors,__EH_FRAME_BEGIN__,__frame_dummy} \
--_SYSTYPE_SVR4 %{mabi=32: -32}%{mabi=n32: -n32}%{mabi=64: -64} %{!mabi*: -n32}"
+-_SYSTYPE_SVR4 %{mabi=32: -32}%{mabi=n32: -n32 %{!mips*:-mips3}}%{mabi=64: -64 %{!mips*:-mips3}} %{!mabi*: -n32 %{!mips*:-mips3}}"
diff -pu gcc/config/mips/mips.c.ORIG gcc/config/mips/mips.c
--- gcc/config/mips/mips.c.ORIG Wed Dec 24 14:06:51 1997
+++ gcc/config/mips/mips.c Wed Mar 25 10:16:24 1998
@@ -3462,10 +3462,8 @@ override_options ()
{
if (mips_abi == ABI_32)
mips_isa = 1;
- else if (mips_abi == ABI_N32)
- mips_isa = 3;
else
- mips_isa = 4;
+ mips_isa = 3;
}
/* If both ABI and ISA were specified, check for conflicts. */
else if (mips_isa_string && mips_abi_string)
diff -u gcc/config/mips/mips.h.ORIG gcc/config/mips/mips.h
--- gcc/config/mips/mips.h.ORIG Wed Dec 24 14:06:54 1997
+++ gcc/config/mips/mips.h Wed Mar 25 10:22:55 1998
@@ -717,7 +717,8 @@
%(subtarget_asm_optimizing_spec) \
%(subtarget_asm_debugging_spec) \
%{membedded-pic} \
-%{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
+%{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32 %{!mips*:-mips3}} \
+%{mabi=64:-64 %{!mips*:-mips3}}%{mabi=n64:-64 %{!mips*:-mips3}} \
%(target_asm_spec) \
%(subtarget_asm_spec)"
@@ -784,9 +785,12 @@
#ifndef CC1_SPEC
#define CC1_SPEC "\
%{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
-%{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
-%{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
-%{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
+%{mabi=n32:%{!mips*:%{!msingle-float:%{!m4650:-mfp64}} -mgp64 -mips3}} \
+%{mabi=64:%{!mips*:%{!msingle-float:%{!m4650:-mfp64}} -mgp64 -mips3}} \
+%{mips1:-mfp32 -mgp32 %{!mabi*:-mabi=32}} \
+%{mips2:-mfp32 -mgp32 %{!mabi*:-mabi=32}} \
+%{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64 %{!mabi*:-mabi=n32}} \
+%{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64 %{!mabi*:-mabi=64}} \
%{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
%{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
%{m4650:-mcpu=r4650} \
diff -u gcc/invoke.texi.ORIG gcc/invoke.texi
--- gcc/invoke.texi.ORIG Tue Dec 2 22:02:05 1997
+++ gcc/invoke.texi Wed Mar 25 11:06:31 1998
@@ -4254,28 +4254,45 @@
These @samp{-m} options are defined for the MIPS family of computers:
@table @code
+@item -mabi=@var{abi type}
+For Irix 6, choose the ABI to target. The choices for @var{abi type} are
+@samp{32}, @samp{n32}, and @samp{64}. With @samp{32}, the default
+instruction level is @samp{-mips1}. With @samp{n32} and @samp{64}, the
+default instruction level is @samp{-mips3}.
+
@item -mcpu=@var{cpu type}
Assume the defaults for the machine type @var{cpu type} when scheduling
instructions. The choices for @var{cpu type} are @samp{r2000}, @samp{r3000},
-@samp{r4000}, @samp{r4400}, @samp{r4600}, and @samp{r6000}. While picking a
-specific @var{cpu type} will schedule things appropriately for that
-particular chip, the compiler will not generate any code that does not
-meet level 1 of the MIPS ISA (instruction set architecture) without
-the @samp{-mips2} or @samp{-mips3} switches being used.
+@samp{r4000}, @samp{r4100}, @samp{r4300}, @samp{r4400}, @samp{r4600},
+@samp{r4650}, @samp{r5000}, @samp{r6000}, and @samp{r8000}. Additionally,
+the @samp{r2000}, @samp{r3000}, @samp{r4000}, @samp{r5000}, and
+@samp{r6000} can be abbreviated as @samp{r2k} (or @samp{r2K}),
+@samp{r3k}, etc. Finally, @samp{orion} is equivalent to @samp{r4600}.
+While picking a specific @var{cpu type} will schedule things appropriately
+for that articular chip, the compiler will not generate any code that does
+not meet level 1 of the MIPS ISA (instruction set architecture) without the
+@samp{-mips2}, @samp{-mips3}, @samp{-mips4}, @samp{-mabi=n32}, or
+@samp{-mabi=64} switches being used.
@item -mips1
Issue instructions from level 1 of the MIPS ISA. This is the default.
-@samp{r3000} is the default @var{cpu type} at this ISA level.
+At this ISA level, @samp{r3000} is the default @var{cpu type} and @samp{32}
+is the default @var{abi type}.
@item -mips2
Issue instructions from level 2 of the MIPS ISA (branch likely, square
-root instructions). @samp{r6000} is the default @var{cpu type} at this
-ISA level.
+root instructions). At this ISA level, @samp{r6000} is the default
+@var{cpu type} and @samp{32} is the default @var{abi type}.
@item -mips3
Issue instructions from level 3 of the MIPS ISA (64 bit instructions).
-@samp{r4000} is the default @var{cpu type} at this ISA level.
-This option does not change the sizes of any of the C data types.
+At this ISA level, @samp{r4000} is the default @var{cpu type} and @samp{n32}
+is the default @var{abi type}.
+
+@item -mips4
+Issue instructions from level 4 of the MIPS ISA (conditional move,
+prefetch, enhanced FPU instructions). At this ISA level, @samp{r8000} is
+the default @var{cpu type} and @samp{64} is the default @var{abi type}.
@item -mfp32
Assume that 32 32-bit floating point registers are available. This is
--
Jerry James
Email: jerry@cs.ucsb.edu
WWW: http://www.cs.ucsb.edu/~jerry/