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Re: Autoincrement addressing modes
- To: michaelh at ongaonga dot chch dot cri dot nz (Michael P. Hayes)
- Subject: Re: Autoincrement addressing modes
- From: Joern Rennecke <amylaar at cygnus dot co dot uk>
- Date: Tue, 17 Mar 1998 00:04:48 +0000 (GMT)
- Cc: rth at cygnus dot com, amylaar at cygnus dot co dot uk, michaelh at ongaonga dot chch dot cri dot nz, egcs at cygnus dot com
> > I thought I'd had a pseudo example of what I'd had in mind for handling
> > both of these in a stroke: referencing it in an insn.
> >
> > (define_insn "*movsi_load"
> > [(set (match_operand:SI 0 "register_operand" "r")
> > (mem:SI (match_address:PI 1 "base,base_disp,auto_inc")))]
> > "ldl %0,%1")
> >
> > (define_insn "*movsi_store"
> > [(set (mem:SI (match_address:PI 1 "base,base_disp,auto_dec"))
> > (match_operand:SI 0 "register_operand" "r"))]
> > "stl %0,%1")
> >
>
> I'm unsure about this since it would require wholesale changes to the
> machine description. For example, how would you handle an add insn
> that could have memory or register operands in various combinations?
Seconded. This even applies to some RISC pattern, e.g. sign/zero extension
can be a register-register operation or a memory-register operation.
The way gcc is designde we have to use a single pattern for this so that
reload can do The Right Thing (tm).