Re: An alpha egcs bug

[hjl at lucon dot org (H.J. Lu)]

> 
> On Wed, Oct 22, 1997 at 12:48:44PM -0700, H.J. Lu wrote:
> > But alpha.md doesn't reflect that detail. With my inline.cc, egcs
> > generates incorrect asm code. Here is my kludge. It seems to work on
> > my test case. I hope someone can find a better fix.
> 

Here is the updated kludge.

> I don't see what your patch changes at all, except to make two patterns
> where once there was one.  The problem is in reload, pure and simple. 

Those 2 patterns have 2 different constraints. They are not the same
because ldl is not symmetric with stl on alpha. With ldl, it is ok
to change the DEST mode from SI to DI. But you cannot do it with
stl.



-- 
H.J. Lu (hjl@gnu.ai.mit.edu)
---
Index: config/alpha/alpha.md
===================================================================
RCS file: /home/work/cvs/gnu/egcs/gcc/config/alpha/alpha.md,v
retrieving revision 1.1.1.5
diff -u -r1.1.1.5 alpha.md
--- alpha.md	1997/10/17 17:13:20	1.1.1.5
+++ alpha.md	1997/10/22 21:24:55
@@ -3631,8 +3631,17 @@
 }")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,f,f,f,m")
-	(match_operand:SI 1 "input_operand" "r,J,I,K,L,m,rJ,f,J,m,fG"))]
+  [(set (match_operand:SI 0 "memory_operand" "m,m")
+	(match_operand:SI 1 "reg_or_0_operand" "rJ,fG"))]
+  "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
+  "@
+   stl %r1,%0
+   sts %R1,%0"
+  [(set_attr "type" "st,st")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,f,f,f")
+	(match_operand:SI 1 "input_operand" "r,J,I,K,L,m,f,J,m"))]
   "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS
    && (register_operand (operands[0], SImode)
        || reg_or_0_operand (operands[1], SImode))"
@@ -3643,12 +3652,10 @@
    lda %0,%1
    ldah %0,%h1
    ldl %0,%1
-   stl %r1,%0
    cpys %1,%1,%0
    cpys $f31,$f31,%0
-   lds %0,%1
-   sts %R1,%0"
-  [(set_attr "type" "ilog,ilog,ilog,iadd,iadd,ld,st,fcpys,fcpys,ld,st")])
+   lds %0,%1"
+  [(set_attr "type" "ilog,ilog,ilog,iadd,iadd,ld,fcpys,fcpys,ld")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,f,f,f,m")