This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.

Index Nav:	[Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav:	[Date Prev] [Date Next]	[Thread Prev] [Thread Next]
Other format:	[Raw text]

[PATCH][AArch64] Fix lane specifier syntax

From: Wilco Dijkstra <Wilco dot Dijkstra at arm dot com>
To: GCC Patches <gcc-patches at gcc dot gnu dot org>
Cc: Richard Earnshaw <Richard dot Earnshaw at arm dot com>, Kyrylo Tkachov <Kyrylo dot Tkachov at arm dot com>, Richard Sandiford <Richard dot Sandiford at arm dot com>
Date: Fri, 6 Mar 2020 15:00:39 +0000
Subject: [PATCH][AArch64] Fix lane specifier syntax
Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none
Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=hlmYkpUkjV3oFFudRpcQbCsvh3qZEEw2izBlFHBDG0I=; b=Rk3sKub9YbTLRo7nvECWswEvAjelk2gEQI1IhOTlBBl2loQQEAP0sOq2zOTV9dbgd7ZaLsXNowD9KJ4JHXgZVmsErmhKlq2zwzbiIrLctllphXUd2B2W81IPDgVejcEVTAvFws/5FazsGSMMkLusPCf9u7TnrDgZlLSbhuHDR0Y/dbG0nxbLX9Vbu54nPsidYky2FbKT3RvDZE0HtU6xqyCXp0MN0MxcORAHNvxysuEHB2hU36iXMmjczeBPQgfzfBEqno6BdrMJQ4e8Gg8q3R6zpp86anFxLtsuQ01A48xe2c5MT7os+oToTcrDFh7IecZqI7xriPmKeqnVpT28BA==
Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=dq1xPRnXp1ph23LOOKaXWIa4y4Bv1Dv5mW54nULZiVasgFpx/QEIX3XV/QtqFN6jndbxlogKEwPa3gUAq9Hkzhs0t8nuYpFN5E3tBdUyHAecWOucICQOdXEFBZH77FDoajUtpM35GgTBTolMKev6nNhrPbAj6c0isuARDcPdCyTC2Sadt/0FOlgUC/JgtGJIntv14YZPgWGJT39iKbQFDtz3sX3cxQPlA3Mko6oqdNF4T27kgve9lV45lO5fS9gREjHHZPwGAgmQr51FkGcX5NcHfsILlCZnO2QFf/cR+4CKcd+EHXcG1cZPujMvSvORitEQAt5Fl8nyfXO8MmJUeQ==
Original-authentication-results: spf=none (sender IP is ) smtp.mailfrom=Wilco dot Dijkstra at arm dot com;

The syntax for lane specifiers uses a vector element rather than a vector:

fmls    v0.2s, v1.2s, v1.s[1]  // rather than v1.2s[2]

Fix all the lane specifiers to use Vetype which uses the correct element type.

Regress&bootstrap pass.

ChangeLog:
2020-03-06  Wilco Dijkstra  <wdijkstr@arm.com>

	* aarch64/aarch64-simd.md (aarch64_mla_elt<mode>): Correct lane syntax.
	(aarch64_mla_elt_<vswap_width_name><mode>): Likewise.
	(aarch64_mls_elt<mode>): Likewise.
	(aarch64_mls_elt_<vswap_width_name><mode>): Likewise.
	(aarch64_fma4_elt<mode>): Likewise.
	(aarch64_fma4_elt_<vswap_width_name><mode>): Likewise.
	(aarch64_fma4_elt_to_64v2df): Likewise.
	(aarch64_fnma4_elt<mode>): Likewise.
	(aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise.
	(aarch64_fnma4_elt_to_64v2df): Likewise.

	* gcc.target/aarch64/fmla_intrinsic_1.c: Check for correct lane syntax.	
	* gcc.target/aarch64/fmls_intrinsic_1.c: Likewise.
	* gcc.target/aarch64/mla_intrinsic_1.c: Likewise.
	* gcc.target/aarch64/mls_intrinsic_1.c: Likewise.

---
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 89aaf8c018e3340dd2d53fc2a6538d3d1220b103..999d80667b7cf06040515958c747d8bca0728acc 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -1350,7 +1350,7 @@ (define_insn "*aarch64_mla_elt<mode>"
  "TARGET_SIMD"
   {
     operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
-    return "mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
+    return "mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
   }
   [(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
 )
@@ -1368,7 +1368,7 @@ (define_insn "*aarch64_mla_elt_<vswap_width_name><mode>"
  "TARGET_SIMD"
   {
     operands[2] = aarch64_endian_lane_rtx (<VSWAP_WIDTH>mode, INTVAL (operands[2]));
-    return "mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
+    return "mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
   }
   [(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
 )
@@ -1408,7 +1408,7 @@ (define_insn "*aarch64_mls_elt<mode>"
  "TARGET_SIMD"
   {
     operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
-    return "mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
+    return "mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
   }
   [(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
 )
@@ -1426,7 +1426,7 @@ (define_insn "*aarch64_mls_elt_<vswap_width_name><mode>"
  "TARGET_SIMD"
   {
     operands[2] = aarch64_endian_lane_rtx (<VSWAP_WIDTH>mode, INTVAL (operands[2]));
-    return "mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
+    return "mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
   }
   [(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
 )
@@ -2003,7 +2003,7 @@ (define_insn "*aarch64_fma4_elt<mode>"
   "TARGET_SIMD"
   {
     operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
-    return "fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
+    return "fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
   }
   [(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
 )
@@ -2020,7 +2020,7 @@ (define_insn "*aarch64_fma4_elt_<vswap_width_name><mode>"
   "TARGET_SIMD"
   {
     operands[2] = aarch64_endian_lane_rtx (<VSWAP_WIDTH>mode, INTVAL (operands[2]));
-    return "fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
+    return "fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
   }
   [(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
 )
@@ -2048,7 +2048,7 @@ (define_insn "*aarch64_fma4_elt_to_64v2df"
   "TARGET_SIMD"
   {
     operands[2] = aarch64_endian_lane_rtx (V2DFmode, INTVAL (operands[2]));
-    return "fmla\\t%0.2d, %3.2d, %1.2d[%2]";
+    return "fmla\\t%0.2d, %3.2d, %1.d[%2]";
   }
   [(set_attr "type" "neon_fp_mla_d_scalar_q")]
 )
@@ -2077,7 +2077,7 @@ (define_insn "*aarch64_fnma4_elt<mode>"
   "TARGET_SIMD"
   {
     operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
-    return "fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
+    return "fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
   }
   [(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
 )
@@ -2095,7 +2095,7 @@ (define_insn "*aarch64_fnma4_elt_<vswap_width_name><mode>"
   "TARGET_SIMD"
   {
     operands[2] = aarch64_endian_lane_rtx (<VSWAP_WIDTH>mode, INTVAL (operands[2]));
-    return "fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
+    return "fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
   }
   [(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
 )
@@ -2125,7 +2125,7 @@ (define_insn "*aarch64_fnma4_elt_to_64v2df"
   "TARGET_SIMD"
   {
     operands[2] = aarch64_endian_lane_rtx (V2DFmode, INTVAL (operands[2]));
-    return "fmls\\t%0.2d, %3.2d, %1.2d[%2]";
+    return "fmls\\t%0.2d, %3.2d, %1.d[%2]";
   }
   [(set_attr "type" "neon_fp_mla_d_scalar_q")]
 )
diff --git a/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c b/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c
index 5b348827002dcfef1f589900a4cf5ff7ada26697..59ad41ed0471b17418c395f31fbe666b60ec3623 100644
--- a/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c
@@ -98,11 +98,11 @@ main (int argc, char **argv)
 
 /* vfma_laneq_f32.
    vfma_lane_f32.  */
-/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s\\\[\[0-9\]+\\\]" 2 } } */
+/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 2 } } */
 
 /* vfmaq_lane_f32.
    vfmaq_laneq_f32.  */
-/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 2 } } */
+/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 2 } } */
 
 /* vfma_lane_f64.  */
 /* { dg-final { scan-assembler-times "fmadd\\td\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+" 1 } } */
@@ -110,6 +110,6 @@ main (int argc, char **argv)
 /* vfmaq_lane_f64.
    vfma_laneq_f64.
    vfmaq_laneq_f64.  */
-/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2?d\\\[\[0-9\]+\\\]" 3 } } */
+/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.d\\\[\[0-9\]+\\\]" 3 } } */
 
 
diff --git a/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c b/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c
index 6c194a023d34ebafb4d732edc303985531f92a63..2d5a3d305360a08a9663cfd497cb1a5374b4b327 100644
--- a/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c
@@ -99,11 +99,11 @@ main (int argc, char **argv)
 
 /* vfms_laneq_f32.
    vfms_lane_f32.  */
-/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s\\\[\[0-9\]+\\\]" 2 } } */
+/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 2 } } */
 
 /* vfmsq_lane_f32.
    vfmsq_laneq_f32.  */
-/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 2 } } */
+/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 2 } } */
 
 /* vfms_lane_f64.  */
 /* { dg-final { scan-assembler-times "fmsub\\td\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+" 1 } } */
@@ -111,6 +111,6 @@ main (int argc, char **argv)
 /* vfmsq_lane_f64.
    vfms_laneq_f64.
    vfmsq_laneq_f64.  */
-/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2?d\\\[\[0-9\]+\\\]" 3 } } */
+/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.d\\\[\[0-9\]+\\\]" 3 } } */
 
 
diff --git a/gcc/testsuite/gcc.target/aarch64/mla_intrinsic_1.c b/gcc/testsuite/gcc.target/aarch64/mla_intrinsic_1.c
index 4bdfac76f401c2b557e024542aa8091d985c0c1c..46b3c78c131ea92eae208d399ef25c71cd8446f7 100644
--- a/gcc/testsuite/gcc.target/aarch64/mla_intrinsic_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/mla_intrinsic_1.c
@@ -78,6 +78,6 @@ main (int argc, char **argv)
   return 0;
 }
 
-/* { dg-final { scan-assembler-times "mla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 4 } } */
-/* { dg-final { scan-assembler-times "mla\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h\\\[\[0-9\]+\\\]" 4 } } */
+/* { dg-final { scan-assembler-times "mla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 4 } } */
+/* { dg-final { scan-assembler-times "mla\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.h\\\[\[0-9\]+\\\]" 4 } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/mls_intrinsic_1.c b/gcc/testsuite/gcc.target/aarch64/mls_intrinsic_1.c
index 4b13fafedcda813004abfc251b98bffeb6cb46e9..e01a4f6d0e1e83cac042a2cad4f02664b87e8c05 100644
--- a/gcc/testsuite/gcc.target/aarch64/mls_intrinsic_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/mls_intrinsic_1.c
@@ -83,6 +83,6 @@ main (int argc, char **argv)
   return 0;
 }
 
-/* { dg-final { scan-assembler-times "mls\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 4 } } */
-/* { dg-final { scan-assembler-times "mls\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h\\\[\[0-9\]+\\\]" 4 } } */
+/* { dg-final { scan-assembler-times "mls\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 4 } } */
+/* { dg-final { scan-assembler-times "mls\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.h\\\[\[0-9\]+\\\]" 4 } } */

Follow-Ups:
- Re: [PATCH][AArch64] Fix lane specifier syntax
  - From: Richard Sandiford

Index Nav:	[Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav:	[Date Prev] [Date Next]	[Thread Prev] [Thread Next]