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[committed] RISC-V: Improve caller-save code generation.
- From: Jim Wilson <jimw at sifive dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: Jim Wilson <jimw at sifive dot com>
- Date: Sat, 8 Feb 2020 14:02:49 -0800
- Subject: [committed] RISC-V: Improve caller-save code generation.
Avoid paradoxical subregs when caller save. This reduces stack frame size
due to smaller loads and stores, and more frequent rematerialization.
Tested with cross riscv32-elf and riscv64-linux build and check, with no
regressions.
Committed.
Jim
PR target/93532
* config/riscv/riscv.h (HARD_REGNO_CALLER_SAVE_MODE): Define.
---
gcc/config/riscv/riscv.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 19438e28fe8..567c23380fe 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -268,6 +268,13 @@ along with GCC; see the file COPYING3. If not see
1, 1 \
}
+/* Select a register mode required for caller save of hard regno REGNO.
+ Contrary to what is documented, the default is not the smallest suitable
+ mode but the largest suitable mode for the given (REGNO, NREGS) pair and
+ it quickly creates paradoxical subregs that can be problematic. */
+#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
+ ((MODE) == VOIDmode ? choose_hard_reg_mode (REGNO, NREGS, NULL) : (MODE))
+
/* Internal macros to classify an ISA register's type. */
#define GP_REG_FIRST 0
--
2.17.1