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Re: [PATCH 2/3] [ARC] Add scaled load pattern
- From: Jeff Law <law at redhat dot com>
- To: Claudiu Zissulescu <claziss at gmail dot com>, gcc-patches at gcc dot gnu dot org
- Cc: fbedard at synopsys dot com, claziss at synopsys dot com, andrew dot burgess at embecosm dot com
- Date: Tue, 19 Nov 2019 17:00:43 -0700
- Subject: Re: [PATCH 2/3] [ARC] Add scaled load pattern
- References: <20191119090250.5619-1-claziss@gmail.com> <20191119090250.5619-2-claziss@gmail.com>
On 11/19/19 2:02 AM, Claudiu Zissulescu wrote:
> ARC processors can use scaled addresses, i.e., the offset part of the
> load address can be shifted by 2 (multiplied by 4). Add this pattern
> and a test for it.
>
> gcc/
> xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
>
> * config/arc/arc.md (load_scaledsi): New pattern.
>
> testcase/
> xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
>
> * gcc.target/arc/scaled-ld.c: New test.
This is worrisome. I'm pretty sure this has to be folded into the
existing move pattern to satisfy obscure reload requirements.
Jeff