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Re: [PATCH v2 3/6] arm: Rename CC_NOOVmode to CC_NZmode

From: "Richard Earnshaw (lists)" <Richard dot Earnshaw at arm dot com>
To: Richard Henderson <richard dot henderson at linaro dot org>, gcc-patches at gcc dot gnu dot org
Cc: kyrylo dot tkachov at arm dot com, richard dot sandiford at arm dot com
Date: Thu, 14 Nov 2019 14:40:39 +0000
Subject: Re: [PATCH v2 3/6] arm: Rename CC_NOOVmode to CC_NZmode
References: <20191114100716.28827-1-richard.henderson@linaro.org> <20191114100716.28827-4-richard.henderson@linaro.org>

On 14/11/2019 10:07, Richard Henderson wrote:

CC_NZmode is a more accurate description of what we require
from the mode, and matches up with the definition in aarch64.

Rename noov_comparison_operator to nz_comparison_operator
in order to match.

	* config/arm/arm-modes.def (CC_NZ): Rename from CC_NOOV.
	* config/arm/predicates.md (nz_comparison_operator): Rename
	from noov_comparison_operator.
	* config/arm/arm.c (arm_select_cc_mode): Use CC_NZmode name.
	(arm_gen_dicompare_reg): Likewise.
	(maybe_get_arm_condition_code): Likewise.
	(thumb1_final_prescan_insn): Likewise.
	(arm_emit_coreregs_64bit_shift): Likewise.
	* config/arm/arm.md (addsi3_compare0): Likewise.
	(*addsi3_compare0_scratch, subsi3_compare0): Likewise.
	(*mulsi3_compare0, *mulsi3_compare0_v6): Likewise.
	(*mulsi3_compare0_scratch, *mulsi3_compare0_scratch_v6): Likewise.
	(*mulsi3addsi_compare0, *mulsi3addsi_compare0_v6): Likewise.
	(*mulsi3addsi_compare0_scratch): Likewise.
	(*mulsi3addsi_compare0_scratch_v6): Likewise.
	(*andsi3_compare0, *andsi3_compare0_scratch): Likewise.
	(*zeroextractsi_compare0_scratch): Likewise.
	(*ne_zeroextractsi, *ne_zeroextractsi_shifted): Likewise.
	(*ite_ne_zeroextractsi, *ite_ne_zeroextractsi_shifted): Likewise.
	(andsi_not_shiftsi_si_scc_no_reuse): Likewise.
	(andsi_not_shiftsi_si_scc): Likewise.
	(*andsi_notsi_si_compare0, *andsi_notsi_si_compare0_scratch): Likewise.
	(*iorsi3_compare0, *iorsi3_compare0_scratch): Likewise.
	(*xorsi3_compare0, *xorsi3_compare0_scratch): Likewise.
	(*shiftsi3_compare0, *shiftsi3_compare0_scratch): Likewise.
	(*not_shiftsi_compare0, *not_shiftsi_compare0_scratch): Likewise.
	(*notsi_compare0, *notsi_compare0_scratch): Likewise.
	(return_addr_mask, *check_arch2): Likewise.
	(*arith_shiftsi_compare0, *arith_shiftsi_compare0_scratch): Likewise.
	(*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch): Likewise.
	(compare_scc splitters): Likewise.
	(movcond_addsi): Likewise.
	* config/arm/thumb2.md (thumb2_addsi3_compare0): Likewise.
	(*thumb2_addsi3_compare0_scratch): Likewise.
	(*thumb2_mulsi_short_compare0): Likewise.
	(*thumb2_mulsi_short_compare0_scratch): Likewise.
	(compare peephole2s): Likewise.
	* config/arm/thumb1.md (thumb1_cbz): Use CC_NZmode and
	nz_comparison_operator names.
	(cbranchsi4_insn): Likewise.


I take it this is a rototill change.  OK.

R.

---
  gcc/config/arm/arm.c         |  12 +--
  gcc/config/arm/arm-modes.def |   4 +-
  gcc/config/arm/arm.md        | 186 +++++++++++++++++------------------
  gcc/config/arm/predicates.md |   2 +-
  gcc/config/arm/thumb1.md     |   8 +-
  gcc/config/arm/thumb2.md     |  34 +++----
  6 files changed, 123 insertions(+), 123 deletions(-)

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 9086cf65953..d996207853c 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -15376,7 +15376,7 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
  	  || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
  	  || GET_CODE (x) == ROTATERT
  	  || (TARGET_32BIT && GET_CODE (x) == ZERO_EXTRACT)))
-    return CC_NOOVmode;
+    return CC_NZmode;

/* A comparison of ~reg with a const is really a special

       canoncialization of compare (~const, reg), which is a reverse
@@ -15492,11 +15492,11 @@ arm_gen_dicompare_reg (rtx_code code, rtx x, rtx y, rtx scratch)
  	      }

rtx clobber = gen_rtx_CLOBBER (VOIDmode, scratch);

-	    cc_reg = gen_rtx_REG (CC_NOOVmode, CC_REGNUM);
+	    cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM);

rtx set

  	      = gen_rtx_SET (cc_reg,
-			     gen_rtx_COMPARE (CC_NOOVmode,
+			     gen_rtx_COMPARE (CC_NZmode,
  					      gen_rtx_IOR (SImode, x_lo, x_hi),
  					      const0_rtx));
  	    emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set,
@@ -23881,7 +23881,7 @@ maybe_get_arm_condition_code (rtx comparison)
  	return code;
        return ARM_NV;

- case E_CC_NOOVmode:

+    case E_CC_NZmode:
        switch (comp_code)
  	{
  	case NE: return ARM_NE;
@@ -25304,7 +25304,7 @@ thumb1_final_prescan_insn (rtx_insn *insn)
  	  cfun->machine->thumb1_cc_insn = insn;
  	  cfun->machine->thumb1_cc_op0 = SET_DEST (set);
  	  cfun->machine->thumb1_cc_op1 = const0_rtx;
-	  cfun->machine->thumb1_cc_mode = CC_NOOVmode;
+	  cfun->machine->thumb1_cc_mode = CC_NZmode;
  	  if (INSN_CODE (insn) == CODE_FOR_thumb1_subsi3_insn)
  	    {
  	      rtx src1 = XEXP (SET_SRC (set), 1);
@@ -30486,7 +30486,7 @@ arm_emit_coreregs_64bit_shift (enum rtx_code code, rtx out, rtx in,
    else
      {
        /* We have a shift-by-register.  */
-      rtx cc_reg = gen_rtx_REG (CC_NOOVmode, CC_REGNUM);
+      rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM);

/* This alternative requires the scratch registers. */

        gcc_assert (scratch1 && REG_P (scratch1));
diff --git a/gcc/config/arm/arm-modes.def b/gcc/config/arm/arm-modes.def
index a6b520df32d..2ce53e0efba 100644
--- a/gcc/config/arm/arm-modes.def
+++ b/gcc/config/arm/arm-modes.def
@@ -29,7 +29,7 @@ ADJUST_FLOAT_FORMAT (HF, ((arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)

/* CCFPEmode should be used with floating inequalities,

     CCFPmode should be used with floating equalities.
-   CC_NOOVmode should be used with SImode integer equalities.
+   CC_NZmode should be used if only the N and Z bits are set correctly.
     CC_Zmode should be used if only the Z flag is set correctly
     CC_Cmode should be used if only the C flag is set correctly, after an
       addition.
@@ -47,7 +47,7 @@ ADJUST_FLOAT_FORMAT (HF, ((arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
       against one of the other operands.
     CCmode should be used otherwise.  */

-CC_MODE (CC_NOOV);

+CC_MODE (CC_NZ);
  CC_MODE (CC_Z);
  CC_MODE (CC_NV);
  CC_MODE (CC_SWP);
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index f1d27ffbb4a..823312e7eac 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -1078,8 +1078,8 @@
  )

(define_insn "addsi3_compare0"

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
  	 (plus:SI (match_operand:SI 1 "s_register_operand" "r, r,r")
  		  (match_operand:SI 2 "arm_add_operand"    "I,L,r"))
  	 (const_int 0)))
@@ -1095,8 +1095,8 @@
  )

(define_insn "*addsi3_compare0_scratch"

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
  	 (plus:SI (match_operand:SI 0 "s_register_operand" "r, r, r")
  		  (match_operand:SI 1 "arm_add_operand"    "I,L, r"))
  	 (const_int 0)))]
@@ -2017,8 +2017,8 @@
  )

(define_insn "subsi3_compare0"

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
  	 (minus:SI (match_operand:SI 1 "arm_rhs_operand" "r,r,I")
  		   (match_operand:SI 2 "arm_rhs_operand" "I,r,r"))
  	 (const_int 0)))
@@ -2256,8 +2256,8 @@
  )

(define_insn "*mulsi3_compare0"

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV (mult:SI
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ (mult:SI
  			  (match_operand:SI 2 "s_register_operand" "r,r")
  			  (match_operand:SI 1 "s_register_operand" "%0,r"))
  			 (const_int 0)))
@@ -2270,8 +2270,8 @@
  )

(define_insn "*mulsi3_compare0_v6"

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV (mult:SI
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ (mult:SI
  			  (match_operand:SI 2 "s_register_operand" "r")
  			  (match_operand:SI 1 "s_register_operand" "r"))
  			 (const_int 0)))
@@ -2284,8 +2284,8 @@
  )

(define_insn "*mulsi_compare0_scratch"

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV (mult:SI
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ (mult:SI
  			  (match_operand:SI 2 "s_register_operand" "r,r")
  			  (match_operand:SI 1 "s_register_operand" "%0,r"))
  			 (const_int 0)))
@@ -2297,8 +2297,8 @@
  )

(define_insn "*mulsi_compare0_scratch_v6"

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV (mult:SI
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ (mult:SI
  			  (match_operand:SI 2 "s_register_operand" "r")
  			  (match_operand:SI 1 "s_register_operand" "r"))
  			 (const_int 0)))
@@ -2310,8 +2310,8 @@
  )

(define_insn "*mulsi3addsi_compare0"

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
  	 (plus:SI (mult:SI
  		   (match_operand:SI 2 "s_register_operand" "r,r,r,r")
  		   (match_operand:SI 1 "s_register_operand" "%0,r,0,r"))
@@ -2327,8 +2327,8 @@
  )

(define_insn "*mulsi3addsi_compare0_v6"

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
  	 (plus:SI (mult:SI
  		   (match_operand:SI 2 "s_register_operand" "r")
  		   (match_operand:SI 1 "s_register_operand" "r"))
@@ -2344,8 +2344,8 @@
  )

(define_insn "*mulsi3addsi_compare0_scratch"

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
  	 (plus:SI (mult:SI
  		   (match_operand:SI 2 "s_register_operand" "r,r,r,r")
  		   (match_operand:SI 1 "s_register_operand" "%0,r,0,r"))
@@ -2359,8 +2359,8 @@
  )

(define_insn "*mulsi3addsi_compare0_scratch_v6"

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
  	 (plus:SI (mult:SI
  		   (match_operand:SI 2 "s_register_operand" "r")
  		   (match_operand:SI 1 "s_register_operand" "r"))
@@ -3004,8 +3004,8 @@
  )

(define_insn "*andsi3_compare0"

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
  	 (and:SI (match_operand:SI 1 "s_register_operand" "r,r,r")
  		 (match_operand:SI 2 "arm_not_operand" "I,K,r"))
  	 (const_int 0)))
@@ -3021,8 +3021,8 @@
  )

(define_insn "*andsi3_compare0_scratch"

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
  	 (and:SI (match_operand:SI 0 "s_register_operand" "r,r,r")
  		 (match_operand:SI 1 "arm_not_operand" "I,K,r"))
  	 (const_int 0)))
@@ -3037,8 +3037,8 @@
  )

(define_insn "*zeroextractsi_compare0_scratch"

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV (zero_extract:SI
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ (zero_extract:SI
  			  (match_operand:SI 0 "s_register_operand" "r")
  			  (match_operand 1 "const_int_operand" "n")
  			  (match_operand 2 "const_int_operand" "n"))
@@ -3078,12 +3078,12 @@
         && INTVAL (operands[2]) > 0
         && INTVAL (operands[2]) + (INTVAL (operands[3]) & 1) <= 8
         && INTVAL (operands[2]) + INTVAL (operands[3]) <= 32)"
-  [(parallel [(set (reg:CC_NOOV CC_REGNUM)
-		   (compare:CC_NOOV (and:SI (match_dup 1) (match_dup 2))
+  [(parallel [(set (reg:CC_NZ CC_REGNUM)
+		   (compare:CC_NZ (and:SI (match_dup 1) (match_dup 2))
  				    (const_int 0)))
  	      (set (match_dup 0) (and:SI (match_dup 1) (match_dup 2)))])
     (set (match_dup 0)
-	(if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0))
+	(if_then_else:SI (eq (reg:CC_NZ CC_REGNUM) (const_int 0))
  			 (match_dup 0) (const_int 1)))]
    "
    operands[2] = GEN_INT (((1 << INTVAL (operands[2])) - 1)
@@ -3108,12 +3108,12 @@
    "TARGET_ARM"
    "#"
    "TARGET_ARM"
-  [(parallel [(set (reg:CC_NOOV CC_REGNUM)
-		   (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
+  [(parallel [(set (reg:CC_NZ CC_REGNUM)
+		   (compare:CC_NZ (ashift:SI (match_dup 1) (match_dup 2))
  				    (const_int 0)))
  	      (set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))])
     (set (match_dup 0)
-	(if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0))
+	(if_then_else:SI (eq (reg:CC_NZ CC_REGNUM) (const_int 0))
  			 (match_dup 0) (const_int 1)))]
    "
    operands[2] = GEN_INT (32 - INTVAL (operands[2]));
@@ -3146,12 +3146,12 @@
         && INTVAL (operands[2]) + (INTVAL (operands[3]) & 1) <= 8
         && INTVAL (operands[2]) + INTVAL (operands[3]) <= 32)
     && !reg_overlap_mentioned_p (operands[0], operands[4])"
-  [(parallel [(set (reg:CC_NOOV CC_REGNUM)
-		   (compare:CC_NOOV (and:SI (match_dup 1) (match_dup 2))
+  [(parallel [(set (reg:CC_NZ CC_REGNUM)
+		   (compare:CC_NZ (and:SI (match_dup 1) (match_dup 2))
  				    (const_int 0)))
  	      (set (match_dup 0) (and:SI (match_dup 1) (match_dup 2)))])
     (set (match_dup 0)
-	(if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0))
+	(if_then_else:SI (eq (reg:CC_NZ CC_REGNUM) (const_int 0))
  			 (match_dup 0) (match_dup 4)))]
    "
    operands[2] = GEN_INT (((1 << INTVAL (operands[2])) - 1)
@@ -3175,12 +3175,12 @@
    "TARGET_ARM && !reg_overlap_mentioned_p (operands[0], operands[3])"
    "#"
    "TARGET_ARM && !reg_overlap_mentioned_p (operands[0], operands[3])"
-  [(parallel [(set (reg:CC_NOOV CC_REGNUM)
-		   (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
+  [(parallel [(set (reg:CC_NZ CC_REGNUM)
+		   (compare:CC_NZ (ashift:SI (match_dup 1) (match_dup 2))
  				    (const_int 0)))
  	      (set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))])
     (set (match_dup 0)
-	(if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0))
+	(if_then_else:SI (eq (reg:CC_NZ CC_REGNUM) (const_int 0))
  			 (match_dup 0) (match_dup 3)))]
    "
    operands[2] = GEN_INT (32 - INTVAL (operands[2]));
@@ -3498,8 +3498,8 @@
  ;; bics output.  Pattern restricts Thumb2 shift operand as bics for Thumb2
  ;; does not support shift by register.
  (define_insn "andsi_not_shiftsi_si_scc_no_reuse"
-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
  		(and:SI (not:SI (match_operator:SI 0 "shift_operator"
  			[(match_operand:SI 1 "s_register_operand" "r,r")
  			 (match_operand:SI 2 "shift_amount_operand" "M,r")]))
@@ -3518,8 +3518,8 @@
  ;; Same as andsi_not_shiftsi_si_scc_no_reuse, but the bics result is also
  ;; getting reused later.
  (define_insn "andsi_not_shiftsi_si_scc"
-  [(parallel [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV
+  [(parallel [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
  		(and:SI (not:SI (match_operator:SI 0 "shift_operator"
  			[(match_operand:SI 1 "s_register_operand" "r,r")
  			 (match_operand:SI 2 "shift_amount_operand" "M,r")]))
@@ -3540,8 +3540,8 @@
  )

(define_insn "*andsi_notsi_si_compare0"

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
  	 (and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
  		 (match_operand:SI 1 "s_register_operand" "r"))
  	 (const_int 0)))
@@ -3554,8 +3554,8 @@
  )

(define_insn "*andsi_notsi_si_compare0_scratch"

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
  	 (and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
  		 (match_operand:SI 1 "s_register_operand" "r"))
  	 (const_int 0)))
@@ -3644,8 +3644,8 @@
  )

(define_insn "*iorsi3_compare0"

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
  	 (ior:SI (match_operand:SI 1 "s_register_operand" "%r,0,r")
  		 (match_operand:SI 2 "arm_rhs_operand" "I,l,r"))
  	 (const_int 0)))
@@ -3660,8 +3660,8 @@
  )

(define_insn "*iorsi3_compare0_scratch"

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
  	 (ior:SI (match_operand:SI 1 "s_register_operand" "%r,0,r")
  		 (match_operand:SI 2 "arm_rhs_operand" "I,l,r"))
  	 (const_int 0)))
@@ -3734,8 +3734,8 @@
  )

(define_insn "*xorsi3_compare0"

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV (xor:SI (match_operand:SI 1 "s_register_operand" "r,r")
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ (xor:SI (match_operand:SI 1 "s_register_operand" "r,r")
  				 (match_operand:SI 2 "arm_rhs_operand" "I,r"))
  			 (const_int 0)))
     (set (match_operand:SI 0 "s_register_operand" "=r,r")
@@ -3747,8 +3747,8 @@
  )

(define_insn "*xorsi3_compare0_scratch"

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV (xor:SI (match_operand:SI 0 "s_register_operand" "r,r")
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ (xor:SI (match_operand:SI 0 "s_register_operand" "r,r")
  				 (match_operand:SI 1 "arm_rhs_operand" "I,r"))
  			 (const_int 0)))]
    "TARGET_32BIT"
@@ -4524,8 +4524,8 @@
  )

(define_insn "*shiftsi3_compare0"

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV (match_operator:SI 3 "shift_operator"
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ (match_operator:SI 3 "shift_operator"
  			  [(match_operand:SI 1 "s_register_operand" "r,r")
  			   (match_operand:SI 2 "arm_rhs_operand" "M,r")])
  			 (const_int 0)))
@@ -4539,8 +4539,8 @@
  )

(define_insn "*shiftsi3_compare0_scratch"

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV (match_operator:SI 3 "shift_operator"
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ (match_operator:SI 3 "shift_operator"
  			  [(match_operand:SI 1 "s_register_operand" "r,r")
  			   (match_operand:SI 2 "arm_rhs_operand" "M,r")])
  			 (const_int 0)))
@@ -4565,8 +4565,8 @@
     (set_attr "type" "mvn_shift,mvn_shift_reg")])

(define_insn "*not_shiftsi_compare0"

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
  	 (not:SI (match_operator:SI 3 "shift_operator"
  		  [(match_operand:SI 1 "s_register_operand" "r,r")
  		   (match_operand:SI 2 "shift_amount_operand" "M,r")]))
@@ -4581,8 +4581,8 @@
     (set_attr "type" "mvn_shift,mvn_shift_reg")])

(define_insn "*not_shiftsi_compare0_scratch"

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
  	 (not:SI (match_operator:SI 3 "shift_operator"
  		  [(match_operand:SI 1 "s_register_operand" "r,r")
  		   (match_operand:SI 2 "shift_amount_operand" "M,r")]))
@@ -5172,8 +5172,8 @@
  )

(define_insn "*notsi_compare0"

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r"))
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ (not:SI (match_operand:SI 1 "s_register_operand" "r"))
  			 (const_int 0)))
     (set (match_operand:SI 0 "s_register_operand" "=r")
  	(not:SI (match_dup 1)))]
@@ -5184,8 +5184,8 @@
  )

(define_insn "*notsi_compare0_scratch"

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r"))
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ (not:SI (match_operand:SI 1 "s_register_operand" "r"))
  			 (const_int 0)))
     (clobber (match_scratch:SI 0 "=r"))]
    "TARGET_32BIT"
@@ -8787,7 +8787,7 @@

(define_expand "return_addr_mask"

    [(set (match_dup 1)
-      (compare:CC_NOOV (unspec [(const_int 0)] UNSPEC_CHECK_ARCH)
+      (compare:CC_NZ (unspec [(const_int 0)] UNSPEC_CHECK_ARCH)
  		       (const_int 0)))
     (set (match_operand:SI 0 "s_register_operand")
        (if_then_else:SI (eq (match_dup 1) (const_int 0))
@@ -8795,12 +8795,12 @@
  		       (const_int 67108860)))] ; 0x03fffffc
    "TARGET_ARM"
    "
-  operands[1] = gen_rtx_REG (CC_NOOVmode, CC_REGNUM);
+  operands[1] = gen_rtx_REG (CC_NZmode, CC_REGNUM);
    ")

(define_insn "*check_arch2"

-  [(set (match_operand:CC_NOOV 0 "cc_register" "")
-      (compare:CC_NOOV (unspec [(const_int 0)] UNSPEC_CHECK_ARCH)
+  [(set (match_operand:CC_NZ 0 "cc_register" "")
+      (compare:CC_NZ (unspec [(const_int 0)] UNSPEC_CHECK_ARCH)
  		       (const_int 0)))]
    "TARGET_ARM"
    "teq\\t%|r0, %|r0\;teq\\t%|pc, %|pc"
@@ -9336,8 +9336,8 @@
    "")

(define_insn "*arith_shiftsi_compare0"

-  [(set (reg:CC_NOOV CC_REGNUM)
-        (compare:CC_NOOV
+  [(set (reg:CC_NZ CC_REGNUM)
+        (compare:CC_NZ
  	 (match_operator:SI 1 "shiftable_operator"
  	  [(match_operator:SI 3 "shift_operator"
  	    [(match_operand:SI 4 "s_register_operand" "r,r")
@@ -9355,8 +9355,8 @@
     (set_attr "type" "alus_shift_imm,alus_shift_reg")])

(define_insn "*arith_shiftsi_compare0_scratch"

-  [(set (reg:CC_NOOV CC_REGNUM)
-        (compare:CC_NOOV
+  [(set (reg:CC_NZ CC_REGNUM)
+        (compare:CC_NZ
  	 (match_operator:SI 1 "shiftable_operator"
  	  [(match_operator:SI 3 "shift_operator"
  	    [(match_operand:SI 4 "s_register_operand" "r,r")
@@ -9386,8 +9386,8 @@
     (set_attr "type" "alus_shift_imm,alus_shift_reg")])

(define_insn "*sub_shiftsi_compare0"

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
  	 (minus:SI (match_operand:SI 1 "s_register_operand" "r,r")
  		   (match_operator:SI 2 "shift_operator"
  		    [(match_operand:SI 3 "s_register_operand" "r,r")
@@ -9404,8 +9404,8 @@
     (set_attr "type" "alus_shift_imm,alus_shift_reg")])

(define_insn "*sub_shiftsi_compare0_scratch"

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
  	 (minus:SI (match_operand:SI 1 "s_register_operand" "r,r")
  		   (match_operator:SI 2 "shift_operator"
  		    [(match_operand:SI 3 "s_register_operand" "r,r")
@@ -9549,11 +9549,11 @@
     (clobber (reg:CC CC_REGNUM))]
    "TARGET_32BIT && reload_completed"
    [(parallel
-    [(set (reg:CC_NOOV CC_REGNUM)
-	  (compare:CC_NOOV (minus:SI (match_dup 1) (match_dup 2))
+    [(set (reg:CC_NZ CC_REGNUM)
+	  (compare:CC_NZ (minus:SI (match_dup 1) (match_dup 2))
  			   (const_int 0)))
       (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
-   (cond_exec (ne:CC_NOOV (reg:CC_NOOV CC_REGNUM) (const_int 0))
+   (cond_exec (ne:CC_NZ (reg:CC_NZ CC_REGNUM) (const_int 0))
  	      (set (match_dup 0) (const_int 1)))])

(define_insn_and_split "*compare_scc"

@@ -10258,8 +10258,8 @@
  )

(define_split

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV (ior:SI
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ (ior:SI
  			  (and:SI (match_operand:SI 0 "s_register_operand" "")
  				  (const_int 1))
  			  (match_operator:SI 1 "arm_comparison_operator"
@@ -10271,14 +10271,14 @@
    [(set (match_dup 4)
  	(ior:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
  		(match_dup 0)))
-   (set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV (and:SI (match_dup 4) (const_int 1))
+   (set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ (and:SI (match_dup 4) (const_int 1))
  			 (const_int 0)))]
    "")

(define_split

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV (ior:SI
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ (ior:SI
  			  (match_operator:SI 1 "arm_comparison_operator"
  			   [(match_operand:SI 2 "s_register_operand" "")
  			    (match_operand:SI 3 "arm_add_operand" "")])
@@ -10290,8 +10290,8 @@
    [(set (match_dup 4)
  	(ior:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
  		(match_dup 0)))
-   (set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV (and:SI (match_dup 4) (const_int 1))
+   (set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ (and:SI (match_dup 4) (const_int 1))
  			 (const_int 0)))]
    "")
  ;; ??? The conditional patterns above need checking for Thumb-2 usefulness
@@ -10380,8 +10380,8 @@
     "TARGET_32BIT"
     "#"
     "&& reload_completed"
-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
  	 (plus:SI (match_dup 3)
  		  (match_dup 4))
  	 (const_int 0)))
diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
index c1f655c7040..6e9263553cc 100644
--- a/gcc/config/arm/predicates.md
+++ b/gcc/config/arm/predicates.md
@@ -430,7 +430,7 @@
  		     (match_operand 0 "arm_vsel_comparison_operator"))
  		(match_operand 0 "expandable_comparison_operator")))

-(define_special_predicate "noov_comparison_operator"

+(define_special_predicate "nz_comparison_operator"
    (match_code "lt,ge,eq,ne"))

(define_special_predicate "minmax_operator"

diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md
index 5c70200bef3..9df793cc47c 100644
--- a/gcc/config/arm/thumb1.md
+++ b/gcc/config/arm/thumb1.md
@@ -1023,9 +1023,9 @@
  	  if (!rtx_equal_p (cfun->machine->thumb1_cc_op0, operands[1])
  	      || !rtx_equal_p (cfun->machine->thumb1_cc_op1, operands[2]))
  	    t = NULL_RTX;
-	  if (cfun->machine->thumb1_cc_mode == CC_NOOVmode)
+	  if (cfun->machine->thumb1_cc_mode == CC_NZmode)
  	    {
-	      if (!noov_comparison_operator (operands[0], VOIDmode))
+	      if (!nz_comparison_operator (operands[0], VOIDmode))
  		t = NULL_RTX;
  	    }
  	  else if (cfun->machine->thumb1_cc_mode != CCmode)
@@ -1097,9 +1097,9 @@
        if (!rtx_equal_p (cfun->machine->thumb1_cc_op0, operands[1])
  	  || !rtx_equal_p (cfun->machine->thumb1_cc_op1, operands[2]))
  	t = NULL_RTX;
-      if (cfun->machine->thumb1_cc_mode == CC_NOOVmode)
+      if (cfun->machine->thumb1_cc_mode == CC_NZmode)
  	{
-	  if (!noov_comparison_operator (operands[0], VOIDmode))
+	  if (!nz_comparison_operator (operands[0], VOIDmode))
  	    t = NULL_RTX;
  	}
        else if (cfun->machine->thumb1_cc_mode != CCmode)
diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md
index 7fce50b045b..2558e404b88 100644
--- a/gcc/config/arm/thumb2.md
+++ b/gcc/config/arm/thumb2.md
@@ -1287,8 +1287,8 @@
  )

(define_insn "thumb2_addsi3_compare0"

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
  	  (plus:SI (match_operand:SI 1 "s_register_operand" "l,  0, r")
  		   (match_operand:SI 2 "arm_add_operand"    "lPt,Ps,rIL"))
  	  (const_int 0)))
@@ -1321,8 +1321,8 @@
  )

(define_insn "*thumb2_addsi3_compare0_scratch"

-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
  	  (plus:SI (match_operand:SI 0 "s_register_operand" "l,  r")
  		   (match_operand:SI 1 "arm_add_operand"    "lPv,rIL"))
  	  (const_int 0)))]
@@ -1359,8 +1359,8 @@
     (set_attr "type" "muls")])

(define_insn "*thumb2_mulsi_short_compare0"

-  [(set (reg:CC_NOOV CC_REGNUM)
-        (compare:CC_NOOV
+  [(set (reg:CC_NZ CC_REGNUM)
+        (compare:CC_NZ
           (mult:SI (match_operand:SI 1 "register_operand" "%0")
  	          (match_operand:SI 2 "register_operand" "l"))
           (const_int 0)))
@@ -1372,8 +1372,8 @@
     (set_attr "type" "muls")])

(define_insn "*thumb2_mulsi_short_compare0_scratch"

-  [(set (reg:CC_NOOV CC_REGNUM)
-        (compare:CC_NOOV
+  [(set (reg:CC_NZ CC_REGNUM)
+        (compare:CC_NZ
           (mult:SI (match_operand:SI 1 "register_operand" "%0")
  	          (match_operand:SI 2 "register_operand" "l"))
           (const_int 0)))
@@ -1477,15 +1477,15 @@
  )

(define_peephole2

-  [(set (match_operand:CC_NOOV 0 "cc_register" "")
-	(compare:CC_NOOV (zero_extract:SI
+  [(set (match_operand:CC_NZ 0 "cc_register" "")
+	(compare:CC_NZ (zero_extract:SI
  			  (match_operand:SI 1 "low_register_operand" "")
  			  (const_int 1)
  			  (match_operand:SI 2 "const_int_operand" ""))
  			 (const_int 0)))
     (match_scratch:SI 3 "l")
     (set (pc)
-	(if_then_else (match_operator:CC_NOOV 4 "equality_operator"
+	(if_then_else (match_operator:CC_NZ 4 "equality_operator"
  		       [(match_dup 0) (const_int 0)])
  		      (match_operand 5 "" "")
  		      (match_operand 6 "" "")))]
@@ -1493,7 +1493,7 @@
     && (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32)
     && peep2_reg_dead_p (2, operands[0])"
    [(parallel [(set (match_dup 0)
-		   (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
+		   (compare:CC_NZ (ashift:SI (match_dup 1) (match_dup 2))
  				    (const_int 0)))
  	      (clobber (match_dup 3))])
     (set (pc)
@@ -1506,15 +1506,15 @@
    ")

(define_peephole2

-  [(set (match_operand:CC_NOOV 0 "cc_register" "")
-	(compare:CC_NOOV (zero_extract:SI
+  [(set (match_operand:CC_NZ 0 "cc_register" "")
+	(compare:CC_NZ (zero_extract:SI
  			  (match_operand:SI 1 "low_register_operand" "")
  			  (match_operand:SI 2 "const_int_operand" "")
  			  (const_int 0))
  			 (const_int 0)))
     (match_scratch:SI 3 "l")
     (set (pc)
-	(if_then_else (match_operator:CC_NOOV 4 "equality_operator"
+	(if_then_else (match_operator:CC_NZ 4 "equality_operator"
  		       [(match_dup 0) (const_int 0)])
  		      (match_operand 5 "" "")
  		      (match_operand 6 "" "")))]
@@ -1522,8 +1522,8 @@
     && (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 32)
     && peep2_reg_dead_p (2, operands[0])"
    [(parallel [(set (match_dup 0)
-		   (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
-				    (const_int 0)))
+		   (compare:CC_NZ (ashift:SI (match_dup 1) (match_dup 2))
+				  (const_int 0)))
  	      (clobber (match_dup 3))])
     (set (pc)
  	(if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)])

References:
- [PATCH v2 0/6] Implement asm flag outputs for arm + aarch64
  - From: Richard Henderson
- [PATCH v2 3/6] arm: Rename CC_NOOVmode to CC_NZmode
  - From: Richard Henderson

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