Re: [RFC PATCH] targetm.omp.device_kind_arch_isa and OpenMP declare variant kind/arch/isa handling

[Szabolcs Nagy <Szabolcs dot Nagy at arm dot com>]

On 30/10/2019 14:48, Jakub Jelinek wrote:
> ARM is an OpenMP member, so if you want, you can participate too.
> https://github.com/OpenMP/spec/issues/2028
> is where I'm trying to track all the declare variant issues that need
> clarification (plus in two examples tickets).

it's unfortunate that neither the mailing list nor
the github repo for the spec are public, i'll try
to get access to them to see the discussions.
thanks for the explanations.

>> for simd variants it means i need to declare the function
>> with the right simd types and attributes.
> 
> For simd it is actually not finished yet, what needs to be done is that
> given the declare simd clauses used as properties of the simd selector
> the FEs use some target hook that will guide it how to transform
> the parameters like targetm.simd_clone.compute_vecsize_and_simdlen
> does and for C tries to just match the types against it and determine
> through that the ABI and perhaps missing simd clauses like
> notinbranch/inbranch, simdlen etc., for C++ actually for each possibility
> will try to construct a call with such arguments and then compare the types.

this omp declare variant mechanism seems fairly complicated.

i need is a way to specify a simd variant unambiguously,
which requires is_inbranch, simd_len and vector_call_abi
setting as far as i can tell (potentially a symbol_name
too if the vector abi mangled name is not good enough).

i think i can extend the simd attribute to do this e.g.

__attribute__((simd("notinbranch", 4, "sse2")))
float expf(float);

would declare the _ZGVbN4v_expf simd variant of expf.
(multiple attributes can be used to declare multiple
variants.)

or

__attribute__((simd("notinbranch", 4, "sse2", "my_vexpf")))
float expf(float);

or maybe

typedef float vfloat __attribute__((vector_size(16)));
vfloat my_vexpf(vfloat);

__attribute__((simd("notinbranch", 4, "sse2", my_vexpf)))
float expf(float);

if we allow custom symbol name for the simd variant.

here "sse2" is not specifying a gcc target nor instruction
set, but the vector call convention, e.g. on x86_64 there
could be "sse2", "avx", "avx2" and "avx512", on aarch64
"advsimd" and "sve".

i thought this would match the omp isa, but based on your
description omp isa will be something else.

there is a further complication that vector length agnostic
(scalable) sve calls need a special simd len value: i'd
reserve 0 for it, but it seems internally that means
'simd len is unset' so that has to change.

i will try to prepare an initial patch for such attribute
to make the proposal more concrete, but if you have any
concerns please let me know.