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Re: [PATCH] Unbreak -masm=intel (PR target/92258)
- From: Uros Bizjak <ubizjak at gmail dot com>
- To: Jakub Jelinek <jakub at redhat dot com>
- Cc: Hongtao Liu <crazylht at gmail dot com>, GCC Patches <gcc-patches at gcc dot gnu dot org>
- Date: Mon, 28 Oct 2019 23:05:59 +0100
- Subject: Re: [PATCH] Unbreak -masm=intel (PR target/92258)
- References: <CAMZc-bxQ5hK9X5rztb_H+KFq46TJGogS0PmsxUMfAtaGt-P4BQ@mail.gmail.com> <20191028220223.GC4650@tucnak>
On Mon, Oct 28, 2019 at 11:02 PM Jakub Jelinek <jakub@redhat.com> wrote:
>
> Hi!
>
> On Sat, Oct 26, 2019 at 09:27:12PM +0800, Hongtao Liu wrote:
> > > BTW: Please also note that there is no need to use <iptr> or operand
> > > mode override in scalar insn templates for intel asm dialect when
> > > operand already has a scalar mode.
> > https://gcc.gnu.org/ml/gcc-patches/2019-10/msg01868.html
> >
> > This patch is to remove redundant <iptr> when operand already has a scalar mode.
> >
> > bootstrap and regression test for i386/x86-64 is ok.
> >
> > Changelog
> > gcc/
> > * config/i386/sse.md (*<sse>_vm<plusminus_insn><mode>3,
> > <sse>_vm<multdiv_mnemonic><mode>3): Remove <iptr> since
> > operand is already scalar mode.
> > (iptr): Remove SF/DF.
>
> SF/DFmode in iptr certainly is not redundant, if you look at tmp-mddump.md
> after this patch, there is <iptr> kept in all the sse.md:3140 patterns:
> (define_insn "<sse>_<unord>comi<round_saeonly_name>"
> [(set (reg:CCFP FLAGS_REG)
> (compare:CCFP
> (vec_select:MODEF
> (match_operand:<ssevecmode> 0 "register_operand" "v")
> (parallel [(const_int 0)]))
> (vec_select:MODEF
> (match_operand:<ssevecmode> 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>")
> (parallel [(const_int 0)]))))]
> "SSE_FLOAT_MODE_P (<MODE>mode)"
> "%v<unord>comi<ssemodesuffix>\t{<round_saeonly_op2>%1, %0|%0, %<iptr>1<round_saeonly_op2>}"
> [(set_attr "type" "ssecomi")
> (set_attr "prefix" "maybe_vex")
> (set_attr "prefix_rep" "0")
> (set (attr "prefix_data16")
> (if_then_else (eq_attr "mode" "DF")
> (const_string "1")
> (const_string "0")))
> (set_attr "mode" "<MODE>")])
> While operands[1] has V2DFmode or V4SFmode and thus not a scalar mode,
> we still want a q or k modifier on it, because that is what the instruction
> actually reads.
>
> The following patch reverts that part, ok for trunk if it passes
> bootstrap/regtest?
>
> 2019-10-28 Jakub Jelinek <jakub@redhat.com>
>
> PR target/92258
> * config/i386/sse.md (iptr): Revert 2019-10-27 change.
>
> * gcc.target/i386/pr92258.c: New test.
OK with a dg-options adjustment.
Thanks,
Uros.
>
> --- gcc/config/i386/sse.md.jj 2019-10-28 22:16:14.619007560 +0100
> +++ gcc/config/i386/sse.md 2019-10-28 22:51:48.594746180 +0100
> @@ -850,7 +850,8 @@ (define_mode_attr iptr
> (V16QI "b") (V8HI "w") (V4SI "k") (V2DI "q")
> (V16SF "k") (V8DF "q")
> (V8SF "k") (V4DF "q")
> - (V4SF "k") (V2DF "q")])
> + (V4SF "k") (V2DF "q")
> + (SF "k") (DF "q")])
>
> ;; Mapping of vector modes to VPTERNLOG suffix
> (define_mode_attr ternlogsuffix
> --- gcc/testsuite/gcc.target/i386/pr92258.c.jj 2019-10-28 22:52:44.093881178 +0100
> +++ gcc/testsuite/gcc.target/i386/pr92258.c 2019-10-28 22:52:40.150942632 +0100
> @@ -0,0 +1,11 @@
> +/* PR target/92258 */
> +/* { dg-do compile } */
> +/* { dg-options "-masm=intel" } */
-msse2 is also needed here for 32bit targets.
> +
> +typedef double V __attribute__ ((__vector_size__ (16)));
> +
> +int
> +foo (V x, V y)
> +{
> + return __builtin_ia32_ucomisdeq (x, y);
> +}
>
>
> Jakub
>