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Re: [AArch64] Strengthen aarch64_hard_regno_call_part_clobbered
- From: Richard Sandiford <richard dot sandiford at arm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: richard dot earnshaw at arm dot com, james dot greenhalgh at arm dot com, marcus dot shawcroft at arm dot com
- Date: Mon, 30 Sep 2019 16:24:15 +0100
- Subject: Re: [AArch64] Strengthen aarch64_hard_regno_call_part_clobbered
- References: <mptzhjc14vu.fsf@arm.com>
Richard Sandiford <richard.sandiford@arm.com> writes:
> The aarch64_vector_pcs handling in aarch64_hard_regno_call_part_clobbered
> checks whether the mode might be bigger than 16 bytes, since on SVE
> targets the (non-SVE) vector PCS only guarantees that the low 16 bytes
> are preserved. But for multi-register modes, we should instead test
> whether each single-register part might be bigger than 16 bytes.
> (The size is always divided evenly between registers.)
>
> The testcase uses XImode as an example where this helps.
>
> Tested on aarch64-linux-gnu (with and without SVE). OK to install?
>
> Richard
>
>
> 2019-09-10 Richard Sandiford <richard.sandiford@arm.com>
>
> gcc/
> * config/aarch64/aarch64.c (aarch64_hard_regno_call_part_clobbered):
> For multi-registers modes, test how big each register part is.
>
> gcc/testsuite/
> * gcc.target/aarch64/torture/simd-abi-8.c: New test.
I've now applied this as r276305.
Thanks,
Richard