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Re: [PATCH][AArch64] Vectorize MULH(R)S patterns with SVE2 instructions
- From: Richard Sandiford <richard dot sandiford at arm dot com>
- To: Yuliang Wang <Yuliang dot Wang at arm dot com>
- Cc: "gcc-patches\@gcc.gnu.org" <gcc-patches at gcc dot gnu dot org>, nd <nd at arm dot com>
- Date: Thu, 12 Sep 2019 11:02:31 +0100
- Subject: Re: [PATCH][AArch64] Vectorize MULH(R)S patterns with SVE2 instructions
- References: <AM0PR08MB3716EE04EE4E4CF5E228C0F49BA20@AM0PR08MB3716.eurprd08.prod.outlook.com> <mpt4l1ykh4s.fsf@arm.com> <AM0PR08MB371664B48ED0B4B4C00CE5D29BB00@AM0PR08MB3716.eurprd08.prod.outlook.com>
Yuliang Wang <Yuliang.Wang@arm.com> writes:
> Hi Richard,
>
> Thanks for your comments and advice; I have applied the relevant changes.
>
> Regards,
> Yuliang
>
>
> UPDATE:
>
> Added new tests. Built and regression tested on aarch64-none-elf and aarch64-linux-gnu.
>
> gcc/ChangeLog:
>
> 2019-09-1 Yuliang Wang <yuliang.wang@arm.com>
>
> PR tree-optimization/89386
>
> * config/aarch64/aarch64-sve2.md (<su>mull<bt><Vwide>)
> (<r>shrnb<mode>, <r>shrnt<mode>): New SVE2 patterns.
> (<su>mulh<r>s<mode>3): New pattern for MULHRS.
> * config/aarch64/iterators.md (UNSPEC_SMULLB, UNSPEC_SMULLT)
> (UNSPEC_UMULLB, UNSPEC_UMULLT, UNSPEC_SHRNB, UNSPEC_SHRNT)
> (UNSPEC_RSHRNB, UNSPEC_RSHRNT, UNSPEC_SMULHS, UNSPEC_SMULHRS)
> UNSPEC_UMULHS, UNSPEC_UMULHRS): New unspecs.
> (MULLBT, SHRNB, SHRNT, MULHRS): New int iterators.
> (su, r): Handle the unspecs above.
> (bt): New int attribute.
> * internal-fn.def (IFN_MULHS, IFN_MULHRS): New internal functions.
> * internal-fn.c (first_commutative_argument): Commutativity info for above.
> * optabs.def (smulhs_optab, smulhrs_optab, umulhs_optab, umulhrs_optab):
> New optabs.
> * doc/md.texi (smulhs$var{m3}, umulhs$var{m3})
> (smulhrs$var{m3}, umulhrs$var{m3}): Documentation for the above.
> * tree-vect-patterns.c (vect_recog_mulhs_pattern): New pattern function.
> (vect_vect_recog_func_ptrs): Add it.
> * testsuite/gcc.target/aarch64/sve2/mulhrs_1.c: New test.
> * testsuite/gcc.dg/vect/vect-mulhrs-1.c: As above.
> * testsuite/gcc.dg/vect/vect-mulhrs-2.c: As above.
> * testsuite/gcc.dg/vect/vect-mulhrs-3.c: As above.
> * testsuite/gcc.dg/vect/vect-mulhrs-4.c: As above.
> * doc/sourcebuild.texi (vect_mulhrs_hi): Document new target selector.
> * testsuite/lib/target-supports.exp (check_effective_target_vect_mulhrs_hi):
> Return true for AArch64 without SVE2.
(with SVE2)
Thanks for doing this. Applied with some very minor whitespace tweaks
as r275682.
Richard