This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
Re: [PATCH][ARM] Cleanup multiply patterns
- From: Wilco Dijkstra <Wilco dot Dijkstra at arm dot com>
- To: GCC Patches <gcc-patches at gcc dot gnu dot org>, Kyrylo Tkachov <Kyrylo dot Tkachov at arm dot com>, Richard Earnshaw <Richard dot Earnshaw at arm dot com>
- Cc: nd <nd at arm dot com>
- Date: Mon, 9 Sep 2019 17:07:32 +0000
- Subject: Re: [PATCH][ARM] Cleanup multiply patterns
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=PqfPOuhiSaMZ7v1Z11juApxwWt9tIEeQi/9bK0zNxV0=; b=FGT+Sc9kkBn/gkW35R9na3BG3yXEfT1cfnDa1v/hMnzZ0Enm+ec20t+4eLm2WMHVcEsVMdOI3J8aj14wlUIJFpxponFi2jxepBrPlVByPyzeDOH+aWccM4QX75cvlXVADzcSh/C7/wyFVFPd0ahm6bgbR7Q12LhREQ90VG0y/qixrocsU2DcftGz53zmfzgndDDifrQifGLlt9Qzi8kNg0jLACMzRyfosKGhSmOVmtxk5lvPWnxzhCVKjAJfKYqgTenDm2hHItz8V+Nfpq4nxFX12OmSg5JwV9Sxl3m9bxWYbREJJI9vqnzni68vHiU1eStVYypt4Lol5iZz6hpzdw==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Y2gmhNprS0s9TxGg1IRLwc0mGHweYdStG+l2kuPPVKkcZfNKyzD95wUQK88FNUlepk0Gn7QgS1tQT3KHfdef6IWLiWTWaoyTogWZjlfY8BR5HWYHFCjYV7lbUSgmuf0R5Nft1yd/ybVOaNlTVTp00UX/BqvMeJo4ZZpNnkZjRvzon+j/DwbK4D2W8l6Y6w3OuF/N7O2Hh4X4bSoUu7g80tqAuAVGymthBXqEv45IRibAOxZBk/lU0heaL1z4ELM/9SIn+kcQRb5CQjrt4XInlGGZEnKwIzqe05ggGwpICqp1XsEuQz20943TlbNllDuO/bb9Z53I0RHzyG/pDP3+Zg==
- Original-authentication-results: spf=none (sender IP is ) smtp.mailfrom=Wilco dot Dijkstra at arm dot com;
- References: <VI1PR0801MB2127244849A5CAE15B11216683B90@VI1PR0801MB2127.eurprd08.prod.outlook.com>
ping
Cleanup the 32-bit multiply patterns. Merge the pre-Armv6 with the Armv6
patterns, remove useless alternatives and order the accumulator operands
to prefer MLA Ra, Rb, Rc, Ra whenever feasible.
Bootstrap OK on armhf, regress passes.
ChangeLog:
2019-09-03 Wilco Dijkstra <wdijkstr@arm.com>
* config/arm/arm.md (arm_mulsi3): Remove pattern.
(arm_mulsi3_v6): Likewise.
(mulsi3addsi_v6): Likewise.
(mulsi3subsi): Likewise.
(mul): Add new multiply pattern.
(mla): Likewise.
(mls): Likewise.
--
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 66dafdc47b7cfc37c131764e482d47bcaab90538..681358512e88f6823d1b6d59038f387daaec226e 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -1594,64 +1594,44 @@ (define_expand "mulsi3"
""
)
-;; Use `&' and then `0' to prevent the operands 0 and 1 being the same
-(define_insn "*arm_mulsi3"
- [(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
- (mult:SI (match_operand:SI 2 "s_register_operand" "r,r")
- (match_operand:SI 1 "s_register_operand" "%0,r")))]
- "TARGET_32BIT && !arm_arch6"
+;; Use `&' and then `0' to prevent operands 0 and 2 being the same
+(define_insn "*mul"
+ [(set (match_operand:SI 0 "s_register_operand" "=l,r,&r,&r")
+ (mult:SI (match_operand:SI 2 "s_register_operand" "l,r,r,r")
+ (match_operand:SI 1 "s_register_operand" "%0,r,0,r")))]
+ "TARGET_32BIT"
"mul%?\\t%0, %2, %1"
[(set_attr "type" "mul")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*arm_mulsi3_v6"
- [(set (match_operand:SI 0 "s_register_operand" "=l,l,r")
- (mult:SI (match_operand:SI 1 "s_register_operand" "0,l,r")
- (match_operand:SI 2 "s_register_operand" "l,0,r")))]
- "TARGET_32BIT && arm_arch6"
- "mul%?\\t%0, %1, %2"
- [(set_attr "type" "mul")
(set_attr "predicable" "yes")
- (set_attr "arch" "t2,t2,*")
+ (set_attr "arch" "t2,v6,nov6,nov6")
(set_attr "length" "4")
- (set_attr "predicable_short_it" "yes,yes,no")]
+ (set_attr "predicable_short_it" "yes,no,*,*")]
)
-;; Unnamed templates to match MLA instruction.
+;; MLA and MLS instruction. Use operand 1 for the accumulator to prefer
+;; reusing the same register.
-(define_insn "*mulsi3addsi"
- [(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r,&r")
+(define_insn "*mla"
+ [(set (match_operand:SI 0 "s_register_operand" "=r,&r,&r,&r")
(plus:SI
- (mult:SI (match_operand:SI 2 "s_register_operand" "r,r,r,r")
- (match_operand:SI 1 "s_register_operand" "%0,r,0,r"))
- (match_operand:SI 3 "s_register_operand" "r,r,0,0")))]
- "TARGET_32BIT && !arm_arch6"
- "mla%?\\t%0, %2, %1, %3"
- [(set_attr "type" "mla")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*mulsi3addsi_v6"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
- (plus:SI
- (mult:SI (match_operand:SI 2 "s_register_operand" "r")
- (match_operand:SI 1 "s_register_operand" "r"))
- (match_operand:SI 3 "s_register_operand" "r")))]
- "TARGET_32BIT && arm_arch6"
- "mla%?\\t%0, %2, %1, %3"
+ (mult:SI (match_operand:SI 3 "s_register_operand" "r,r,r,r")
+ (match_operand:SI 2 "s_register_operand" "%r,r,0,r"))
+ (match_operand:SI 1 "s_register_operand" "r,0,r,r")))]
+ "TARGET_32BIT"
+ "mla%?\\t%0, %3, %2, %1"
[(set_attr "type" "mla")
- (set_attr "predicable" "yes")]
+ (set_attr "predicable" "yes")
+ (set_attr "arch" "v6,nov6,nov6,nov6")]
)
-(define_insn "*mulsi3subsi"
+(define_insn "*mls"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(minus:SI
- (match_operand:SI 3 "s_register_operand" "r")
- (mult:SI (match_operand:SI 2 "s_register_operand" "r")
- (match_operand:SI 1 "s_register_operand" "r"))))]
+ (match_operand:SI 1 "s_register_operand" "r")
+ (mult:SI (match_operand:SI 3 "s_register_operand" "r")
+ (match_operand:SI 2 "s_register_operand" "r"))))]
"TARGET_32BIT && arm_arch_thumb2"
- "mls%?\\t%0, %2, %1, %3"
+ "mls%?\\t%0, %3, %2, %1"
[(set_attr "type" "mla")
(set_attr "predicable" "yes")]
)