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Re: [PATCH] Sanitizing the middle-end interface to the back-end for strict alignment


On 8/28/19 2:07 PM, Christophe Lyon wrote:
> Hi,
> 
> This patch causes an ICE when building libgcc's unwind-arm.o
> when configuring GCC:
> --target  arm-none-linux-gnueabihf --with-mode thumb --with-cpu
> cortex-a15 --with-fpu neon-vfpv4:
> 
> The build works for the same target, but --with-mode arm --with-cpu
> cortex a9 --with-fpu vfp
> 
> In file included from
> /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/libgcc/config/arm/unwind-arm.c:144:
> /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/libgcc/unwind-arm-common.inc:
> In function 'get_eit_entry':
> /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/libgcc/unwind-arm-common.inc:245:29:
> warning: cast discards 'const' qualifier from pointer target type
> [-Wcast-qual]
>   245 |       ucbp->pr_cache.ehtp = (_Unwind_EHT_Header *)&eitp->content;
>       |                             ^
> during RTL pass: expand
> /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/libgcc/unwind-arm-common.inc:
> In function 'unwind_phase2_forced':
> /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/libgcc/unwind-arm-common.inc:319:18:
> internal compiler error: in gen_movdi, at config/arm/arm.md:5235
>   319 |   saved_vrs.core = entry_vrs->core;
>       |   ~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~
> 0x126530f gen_movdi(rtx_def*, rtx_def*)
>         /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/config/arm/arm.md:5235
> 0x896d92 insn_gen_fn::operator()(rtx_def*, rtx_def*) const
>         /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/recog.h:318
> 0x896d92 emit_move_insn_1(rtx_def*, rtx_def*)
>         /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/expr.c:3694
> 0x897083 emit_move_insn(rtx_def*, rtx_def*)
>         /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/expr.c:3790
> 0xfc25d6 gen_cpymem_ldrd_strd(rtx_def**)
>         /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/config/arm/arm.c:14582
> 0x126a1f1 gen_cpymemqi(rtx_def*, rtx_def*, rtx_def*, rtx_def*)
>         /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/config/arm/arm.md:6688
> 0xb0bc08 maybe_expand_insn(insn_code, unsigned int, expand_operand*)
>         /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/optabs.c:7440
> 0x89ba1e emit_block_move_via_cpymem
>         /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/expr.c:1808
> 0x89ba1e emit_block_move_hints(rtx_def*, rtx_def*, rtx_def*,
> block_op_methods, unsigned int, long, unsigned long, unsigned long,
> unsigned long, bool, bool*)
>         /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/expr.c:1627
> 0x89c383 emit_block_move(rtx_def*, rtx_def*, rtx_def*, block_op_methods)
>         /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/expr.c:1667
> 0x89fb4e store_expr(tree_node*, rtx_def*, int, bool, bool)
>         /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/expr.c:5845
> 0x88c1f9 store_field
>         /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/expr.c:7149
> 0x8a0c22 expand_assignment(tree_node*, tree_node*, bool)
>         /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/expr.c:5304
> 0x761964 expand_gimple_stmt_1
>         /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/cfgexpand.c:3779
> 0x761964 expand_gimple_stmt
>         /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/cfgexpand.c:3875
> 0x768583 expand_gimple_basic_block
>         /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/cfgexpand.c:5915
> 0x76abc6 execute
>         /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/cfgexpand.c:6538
> 
> Christophe
> 

Okay, sorry for the breakage.

What is happening in gen_cpymem_ldrd_strd is of course against the rules:

It uses emit_move_insn on only 4-byte aligned DI-mode memory operands.

I have a patch for this, which is able to fix the libgcc build on a cross, but have no
possibility to bootstrap the affected target.

Could you please help?


Thanks
Bernd.
2019-08-28  Bernd Edlinger  <bernd.edlinger@hotmail.de>

	* config/arm/arm.md (unaligned_loaddi,
	unaligned_storedi): New unspec insn patterns.
	* config/arm/arm.c (gen_cpymem_ldrd_strd): Use unaligned_loaddi
	and unaligned_storedi for 4-byte aligned memory.

Index: gcc/config/arm/arm.c
===================================================================
--- gcc/config/arm/arm.c	(revision 274987)
+++ gcc/config/arm/arm.c	(working copy)
@@ -14578,8 +14578,10 @@ gen_cpymem_ldrd_strd (rtx *operands)
 	  low_reg = gen_lowpart (SImode, reg0);
 	  hi_reg = gen_highpart_mode (SImode, DImode, reg0);
 	}
-      if (src_aligned)
-        emit_move_insn (reg0, src);
+      if (MEM_ALIGN (src) >= 2 * BITS_PER_WORD)
+	emit_move_insn (reg0, src);
+      else if (src_aligned)
+	emit_insn (gen_unaligned_loaddi (reg0, src));
       else
 	{
 	  emit_insn (gen_unaligned_loadsi (low_reg, src));
@@ -14587,8 +14589,10 @@ gen_cpymem_ldrd_strd (rtx *operands)
 	  emit_insn (gen_unaligned_loadsi (hi_reg, src));
 	}
 
-      if (dst_aligned)
-        emit_move_insn (dst, reg0);
+      if (MEM_ALIGN (dst) >= 2 * BITS_PER_WORD)
+	emit_move_insn (dst, reg0);
+      else if (dst_aligned)
+	emit_insn (gen_unaligned_storedi (dst, reg0));
       else
 	{
 	  emit_insn (gen_unaligned_storesi (dst, low_reg));
Index: gcc/config/arm/arm.md
===================================================================
--- gcc/config/arm/arm.md	(revision 274987)
+++ gcc/config/arm/arm.md	(working copy)
@@ -3963,6 +3963,17 @@
 
 ; ARMv6+ unaligned load/store instructions (used for packed structure accesses).
 
+(define_insn "unaligned_loaddi"
+  [(set (match_operand:DI 0 "s_register_operand" "=r")
+	(unspec:DI [(match_operand:DI 1 "memory_operand" "m")]
+		   UNSPEC_UNALIGNED_LOAD))]
+  "TARGET_32BIT && TARGET_LDRD"
+  "*
+  return output_move_double (operands, true, NULL);
+  "
+  [(set_attr "length" "8")
+   (set_attr "type" "load_8")])
+
 (define_insn "unaligned_loadsi"
   [(set (match_operand:SI 0 "s_register_operand" "=l,l,r")
 	(unspec:SI [(match_operand:SI 1 "memory_operand" "m,Uw,m")]
@@ -4008,6 +4019,17 @@
    (set_attr "predicable_short_it" "no,yes,no")
    (set_attr "type" "load_byte")])
 
+(define_insn "unaligned_storedi"
+  [(set (match_operand:DI 0 "memory_operand" "=m")
+	(unspec:DI [(match_operand:DI 1 "s_register_operand" "r")]
+		   UNSPEC_UNALIGNED_STORE))]
+  "TARGET_32BIT && TARGET_LDRD"
+  "*
+  return output_move_double (operands, true, NULL);
+  "
+  [(set_attr "length" "8")
+   (set_attr "type" "store_8")])
+
 (define_insn "unaligned_storesi"
   [(set (match_operand:SI 0 "memory_operand" "=m,Uw,m")
 	(unspec:SI [(match_operand:SI 1 "s_register_operand" "l,l,r")]

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