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[PATCH][Arm] Add support for missing CPUs

Hi all,

This patch adds '-mcpu' options for following CPUs:
Cortex-M35P, Cortex-A77, Cortex-A76AE.

Related specifications are as following:

Bootstraped/Regtested for arm-none-linux-gnueabihf.

Please help to check.



2019-07-29  Dennis Zhang  <>

	* config/arm/ New entries for Cortex-M35P,
	Cortex-A76AE and Cortex-A77.
	* config/arm/arm-tables.opt: Regenerated.
	* config/arm/ Likewise.
	* doc/invoke.texi: Document the added processors.
diff --git a/gcc/config/arm/ b/gcc/config/arm/
index 3a55f6ac6d2..f8a3b3db67a 100644
--- a/gcc/config/arm/
+++ b/gcc/config/arm/
@@ -1331,6 +1331,28 @@ begin cpu cortex-a76
  part d0b
 end cpu cortex-a76
+begin cpu cortex-a76ae
+ cname cortexa76ae
+ tune for cortex-a57
+ tune flags LDSCHED
+ architecture armv8.2-a+fp16+dotprod+simd
+ option crypto add FP_ARMv8 CRYPTO
+ costs cortex_a57
+ vendor 41
+ part d0e
+end cpu cortex-a76ae
+begin cpu cortex-a77
+ cname cortexa77
+ tune for cortex-a57
+ tune flags LDSCHED
+ architecture armv8.2-a+fp16+dotprod+simd
+ option crypto add FP_ARMv8 CRYPTO
+ costs cortex_a57
+ vendor 41
+ part d0d
+end cpu cortex-a77
 begin cpu neoverse-n1
  cname neoversen1
  alias !ares
@@ -1379,6 +1401,15 @@ begin cpu cortex-m33
  costs v7m
 end cpu cortex-m33
+begin cpu cortex-m35p
+ cname cortexm35p
+ tune flags LDSCHED
+ architecture armv8-m.main+dsp+fp
+ option nofp remove ALL_FP
+ option nodsp remove armv7em
+ costs v7m
+end cpu cortex-m35p
 # V8 R-profile implementations.
 begin cpu cortex-r52
  cname cortexr52
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index bba54aea3d6..aeb5b3fbf62 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -234,6 +234,12 @@ Enum(processor_type) String(cortex-a75) Value( TARGET_CPU_cortexa75)
 Enum(processor_type) String(cortex-a76) Value( TARGET_CPU_cortexa76)
+Enum(processor_type) String(cortex-a76ae) Value( TARGET_CPU_cortexa76ae)
+Enum(processor_type) String(cortex-a77) Value( TARGET_CPU_cortexa77)
 Enum(processor_type) String(neoverse-n1) Value( TARGET_CPU_neoversen1)
@@ -249,6 +255,9 @@ Enum(processor_type) String(cortex-m23) Value( TARGET_CPU_cortexm23)
 Enum(processor_type) String(cortex-m33) Value( TARGET_CPU_cortexm33)
+Enum(processor_type) String(cortex-m35p) Value( TARGET_CPU_cortexm35p)
 Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52)
diff --git a/gcc/config/arm/ b/gcc/config/arm/
index b9dfb66ec84..6fa5bb27750 100644
--- a/gcc/config/arm/
+++ b/gcc/config/arm/
@@ -44,7 +44,8 @@
-	cortexa76,neoversen1,cortexa75cortexa55,
-	cortexa76cortexa55,cortexm23,cortexm33,
+	cortexa76,cortexa76ae,cortexa77,
+	neoversen1,cortexa75cortexa55,cortexa76cortexa55,
+	cortexm23,cortexm33,cortexm35p,
 	(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 29585cf15aa..42a9d7f81ed 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -17510,10 +17510,12 @@ Permissible names are: @samp{arm7tdmi}, @samp{arm7tdmi-s}, @samp{arm710t},
 @samp{cortex-a9}, @samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a17},
 @samp{cortex-a32}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55},
 @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75},
-@samp{cortex-a76}, @samp{ares}, @samp{cortex-r4}, @samp{cortex-r4f},
+@samp{cortex-a76}, @samp{cortex-a76ae}, @samp{cortex-a77},
+@samp{ares}, @samp{cortex-r4}, @samp{cortex-r4f},
 @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-r52},
 @samp{cortex-m0}, @samp{cortex-m0plus}, @samp{cortex-m1}, @samp{cortex-m3},
 @samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m23}, @samp{cortex-m33},
 @samp{cortex-m1.small-multiply}, @samp{cortex-m0.small-multiply},
 @samp{cortex-m0plus.small-multiply}, @samp{exynos-m1}, @samp{marvell-pj4},
 @samp{neoverse-n1}, @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2},
@@ -17577,14 +17579,14 @@ The following extension options are common to the listed CPUs:
 @table @samp
 @item +nodsp
-Disable the DSP instructions on @samp{cortex-m33}.
+Disable the DSP instructions on @samp{cortex-m33}, @samp{cortex-m35p}.
 @item  +nofp
 Disables the floating-point instructions on @samp{arm9e},
 @samp{arm946e-s}, @samp{arm966e-s}, @samp{arm968e-s}, @samp{arm10e},
 @samp{arm1020e}, @samp{arm1022e}, @samp{arm926ej-s},
 @samp{arm1026ej-s}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8},
-@samp{cortex-m4}, @samp{cortex-m7} and @samp{cortex-m33}.
+@samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m33} and @samp{cortex-m35p}.
 Disables the floating-point and SIMD instructions on
 @samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7},
 @samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a12},

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