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PowerPC 'future' patches introduction

I will be submitting 10 patches will that will add support to GCC for a
possible future PowerPC processor.  These patches add support for new
instructions that extend the offsettable memory instructions (D, DS, or DQ
instruction formats) to have 34 bit offsets (instead of 16, 14, or 12 bits
respectively).  These instructions use reserved encodings for the first 32 bits
and the second 32 bits may either be the traditional instruction that is being
extended or a new encoding.  These new 64-bit instructions are called
'prefixed' instructions.

These new instructions also have a mode that uses the 34 bit offset and adds it
to the current location instead of a base register, giving pc-relative
addressing.  Pc-relative addressing will be supported in the next ABI (3.1) as
an alternative to the current TOC based addressing.

The first patch adds the new insn_form enumeration to describe the instruction
format.  This is similar to the previous patch, except the name is now
insn_form instead of offset_format, and I simplified the set up for the
instruction format, using the existing reg_addr structure.

The second patch adds the basic infrastructure using RTL attributes on the
insns to say whether an instructin is prefixed or not.  I tried to simplify
this over previous versions of patch, by only having a "prefixed" attribute
instead of a "maybe_prefixed" and "prefixed" attributes.

The third patch adds support for all offsettable memory instructions to use the
new instructions.  After this patch is installed, you would be able to generate
the new pc-relative instructions if you use the -mpcrel option.

The fourth patch adjusts the costs when you use prefixed instructions (prefixed
instructions are larger than traditional instructions, so we need to adjust the
costs based on instruction size).

The fifth patch switches the default when you use -mcpu=future to use
pc-relative instructions instead of using the TOC by default.

The sixth patch adds support for the 'future' machine to the target_clones and
target function attributes, as well as the __builtin_cpu_supports built in

The seventh patch adds a new RTL pass to implement the PCREL_OPT relocations
that will be part of the ISA 3.1 specification.  This optimization allows the
linker to optimize accessing external symbols that are local to the main
program in some cases.

The eighth, ninth, and tenth passes adds tests for the 'future' machine to the

After these patches are installed, Alan Modra will have a set of patches update
the thread local storage (TLS) for use with pc-relative addressing.

Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email:, phone: +1 (978) 899-4797

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