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[PATCH v2 02/18] Use CONST_INT_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh CONST_INT


2019-08-05  Arvind Sankar  <nivedita@alum.mit.edu>

	gcc/ChangeLog:

	* combine.c: Convert GET_CODE (..) == CONST_INT to
	CONST_INT_P (..).
	* config/aarch64/aarch64.c: Likewise.
	* config/aarch64/predicates.md: Likewise.
	* config/arc/arc.c: Likewise.
	* config/arc/arc.h: Likewise.
	* config/arc/fpx.md: Likewise.
	* config/arc/predicates.md: Likewise.
	* config/bfin/bfin.c: Likewise.
	* config/bfin/bfin.md: Likewise.
	* config/bfin/predicates.md: Likewise.
	* config/c6x/c6x.c: Likewise.
	* config/c6x/c6x.md: Likewise.
	* config/c6x/predicates.md: Likewise.
	* config/cr16/cr16.c: Likewise.
	* config/cr16/cr16.h: Likewise.
	* config/cr16/cr16.md: Likewise.
	* config/cr16/predicates.md: Likewise.
	* config/cris/cris.md: Likewise.
	* config/csky/csky.c: Likewise.
	* config/csky/csky.md: Likewise.
	* config/csky/predicates.md: Likewise.
	* config/darwin.c: Likewise.
	* config/epiphany/epiphany.c: Likewise.
	* config/epiphany/epiphany.h: Likewise.
	* config/fr30/fr30.c: Likewise.
	* config/fr30/fr30.h: Likewise.
	* config/fr30/fr30.md: Likewise.
	* config/fr30/predicates.md: Likewise.
	* config/frv/frv.c: Likewise.
	* config/frv/frv.h: Likewise.
	* config/frv/frv.md: Likewise.
	* config/frv/predicates.md: Likewise.
	* config/ft32/constraints.md: Likewise.
	* config/ft32/predicates.md: Likewise.
	* config/gcn/gcn-valu.md: Likewise.
	* config/gcn/gcn.c: Likewise.
	* config/gcn/gcn.md: Likewise.
	* config/h8300/h8300.c: Likewise.
	* config/h8300/h8300.h: Likewise.
	* config/h8300/h8300.md: Likewise.
	* config/h8300/predicates.md: Likewise.
	* config/ia64/ia64.c: Likewise.
	* config/ia64/ia64.md: Likewise.
	* config/ia64/predicates.md: Likewise.
	* config/ia64/vect.md: Likewise.
	* config/iq2000/iq2000.c: Likewise.
	* config/iq2000/iq2000.h: Likewise.
	* config/iq2000/iq2000.md: Likewise.
	* config/iq2000/predicates.md: Likewise.
	* config/lm32/lm32.c: Likewise.
	* config/lm32/lm32.h: Likewise.
	* config/lm32/lm32.md: Likewise.
	* config/m32c/m32c.c: Likewise.
	* config/m32c/muldiv.md: Likewise.
	* config/m32c/predicates.md: Likewise.
	* config/m68k/m68k.c: Likewise.
	* config/m68k/m68k.h: Likewise.
	* config/m68k/m68k.md: Likewise.
	* config/m68k/predicates.md: Likewise.
	* config/mcore/mcore.c: Likewise.
	* config/mcore/mcore.md: Likewise.
	* config/mcore/predicates.md: Likewise.
	* config/microblaze/microblaze.c: Likewise.
	* config/microblaze/microblaze.md: Likewise.
	* config/microblaze/predicates.md: Likewise.
	* config/mmix/mmix.c: Likewise.
	* config/mmix/mmix.md: Likewise.
	* config/mmix/predicates.md: Likewise.
	* config/moxie/moxie.c: Likewise.
	* config/moxie/predicates.md: Likewise.
	* config/msp430/msp430.c: Likewise.
	* config/msp430/msp430.md: Likewise.
	* config/nds32/nds32-cost.c: Likewise.
	* config/nds32/nds32-intrinsic.c: Likewise.
	* config/nds32/nds32-md-auxiliary.c: Likewise.
	* config/nds32/nds32-memory-manipulation.c: Likewise.
	* config/nds32/nds32-multiple.md: Likewise.
	* config/nds32/nds32-pipelines-auxiliary.c: Likewise.
	* config/nds32/nds32-predicates.c: Likewise.
	* config/nds32/nds32-utils.c: Likewise.
	* config/nds32/nds32.c: Likewise.
	* config/nios2/nios2.c: Likewise.
	* config/nvptx/nvptx.c: Likewise.
	* config/pa/pa.c: Likewise.
	* config/pa/pa.h: Likewise.
	* config/pa/pa.md: Likewise.
	* config/pa/predicates.md: Likewise.
	* config/pdp11/pdp11.c: Likewise.
	* config/pdp11/pdp11.md: Likewise.
	* config/pru/pru.c: Likewise.
	* config/pru/pru.md: Likewise.
	* config/riscv/riscv.c: Likewise.
	* config/riscv/riscv.md: Likewise.
	* config/rl78/rl78.c: Likewise.
	* config/rs6000/rs6000.c: Likewise.
	* config/rx/rx.c: Likewise.
	* config/rx/rx.md: Likewise.
	* config/s390/predicates.md: Likewise.
	* config/s390/s390.c: Likewise.
	* config/s390/s390.md: Likewise.
	* config/sparc/predicates.md: Likewise.
	* config/sparc/sparc.c: Likewise.
	* config/sparc/sparc.md: Likewise.
	* config/spu/constraints.md: Likewise.
	* config/spu/predicates.md: Likewise.
	* config/spu/spu-builtins.md: Likewise.
	* config/spu/spu.c: Likewise.
	* config/spu/spu.md: Likewise.
	* config/stormy16/predicates.md: Likewise.
	* config/v850/predicates.md: Likewise.
	* config/v850/v850.c: Likewise.
	* config/v850/v850.md: Likewise.
	* config/visium/visium.c: Likewise.
	* config/xtensa/xtensa.c: Likewise.
	* config/xtensa/xtensa.h: Likewise.
	* cse.c: Likewise.
	* dwarf2out.c: Likewise.
	* explow.c: Likewise.
	* expr.c: Likewise.
	* genrecog.c: Likewise.
	* ree.c: Likewise.
	* reload1.c: Likewise.
	* tree-ssa-address.c: Likewise.
	* var-tracking.c: Likewise.

 124 files changed, 933 insertions(+), 933 deletions(-)

diff --git a/gcc/combine.c b/gcc/combine.c
index f7b1ebc8cc0..1c59ab54a40 100644
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -5361,7 +5361,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
 	 constant.  It may be better to try splitting (plus (mult B -C) A)
 	 instead if this isn't a multiply by a power of two.  */
       if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
-	  && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
+	  && CONST_INT_P (XEXP (XEXP (x, 1), 1))
 	  && !pow2p_hwi (INTVAL (XEXP (XEXP (x, 1), 1))))
 	{
 	  machine_mode mode = GET_MODE (x);
@@ -5382,7 +5382,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
       if (!set_src
 	  && (GET_CODE (XEXP (x, 0)) == MULT
 	      || (GET_CODE (XEXP (x, 0)) == ASHIFT
-		  && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
+		  && CONST_INT_P (XEXP (XEXP (x, 0), 1)))))
         return loc;
 
     default:
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 5bf182ccc0c..a526b8be522 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -2807,7 +2807,7 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
 bool
 aarch64_mov128_immediate (rtx imm)
 {
-  if (GET_CODE (imm) == CONST_INT)
+  if (CONST_INT_P (imm))
     return true;
 
   gcc_assert (CONST_WIDE_INT_NUNITS (imm) == 2);
@@ -7148,7 +7148,7 @@ aarch64_can_const_movi_rtx_p (rtx x, machine_mode mode)
 
       imode = int_mode_for_mode (mode).require ();
     }
-  else if (GET_CODE (x) == CONST_INT
+  else if (CONST_INT_P (x)
 	   && is_a <scalar_int_mode> (mode, &imode))
     ival = INTVAL (x);
   else
diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md
index 10100ca830a..9f2e139899f 100644
--- a/gcc/config/aarch64/predicates.md
+++ b/gcc/config/aarch64/predicates.md
@@ -265,7 +265,7 @@
       op = XEXP (op, 0);
       if (GET_CODE (op) != PLUS
 	  || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
-	  || GET_CODE (XEXP (op, 1)) != CONST_INT)
+	  || !CONST_INT_P (XEXP (op, 1)))
 	return false;
       op = XEXP (op, 0);
       /* FALLTHRU */
@@ -287,7 +287,7 @@
       op = XEXP (op, 0);
       if (GET_CODE (op) != PLUS
 	  || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
-	  || GET_CODE (XEXP (op, 1)) != CONST_INT)
+	  || !CONST_INT_P (XEXP (op, 1)))
 	return false;
       op = XEXP (op, 0);
       /* FALLTHRU */
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 3c4d89cdd08..486053c98ca 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -90,7 +90,7 @@ HARD_REG_SET overrideregs;
 /* Check if an rtx fits in the store instruction format.  Loads can
    handle any constant.  */
 #define RTX_OK_FOR_OFFSET_P(MODE, X)					\
-  (GET_CODE (X) == CONST_INT						\
+  (CONST_INT_P (X)						\
    && SMALL_INT_RANGE (INTVAL (X), (GET_MODE_SIZE (MODE) - 1) & (~0x03), \
 		       (INTVAL (X) & (GET_MODE_SIZE (MODE) - 1) & 3	\
 			? 0						\
@@ -4179,7 +4179,7 @@ output_shift (rtx *operands)
     default:       gcc_unreachable ();
     }
 
-  if (GET_CODE (operands[2]) != CONST_INT)
+  if (!CONST_INT_P (operands[2]))
     {
       output_asm_insn ("and.f lp_count,%2, 0x1f", operands);
       goto shiftloop;
@@ -4436,7 +4436,7 @@ arc_print_operand (FILE *file, rtx x, int code)
   switch (code)
     {
     case 'Z':
-      if (GET_CODE (x) == CONST_INT)
+      if (CONST_INT_P (x))
 	fprintf (file, "%d",exact_log2(INTVAL (x) + 1) - 1 );
       else
 	output_operand_lossage ("invalid operand to %%Z code");
@@ -4444,7 +4444,7 @@ arc_print_operand (FILE *file, rtx x, int code)
       return;
 
     case 'z':
-      if (GET_CODE (x) == CONST_INT)
+      if (CONST_INT_P (x))
 	fprintf (file, "%d",exact_log2 (INTVAL (x) & 0xffffffff));
       else
 	output_operand_lossage ("invalid operand to %%z code");
@@ -4452,7 +4452,7 @@ arc_print_operand (FILE *file, rtx x, int code)
       return;
 
     case 'c':
-      if (GET_CODE (x) == CONST_INT)
+      if (CONST_INT_P (x))
         fprintf (file, "%ld", INTVAL (x) );
       else
         output_operand_lossage ("invalid operands to %%c code");
@@ -4460,7 +4460,7 @@ arc_print_operand (FILE *file, rtx x, int code)
       return;
 
     case 'M':
-      if (GET_CODE (x) == CONST_INT)
+      if (CONST_INT_P (x))
 	fprintf (file, "%d",exact_log2(~INTVAL (x)) );
       else
 	output_operand_lossage ("invalid operand to %%M code");
@@ -4468,14 +4468,14 @@ arc_print_operand (FILE *file, rtx x, int code)
       return;
 
     case 'p':
-      if (GET_CODE (x) == CONST_INT)
+      if (CONST_INT_P (x))
 	fprintf (file, "%d", exact_log2 (INTVAL (x) & -INTVAL (x)));
       else
 	output_operand_lossage ("invalid operand to %%p code");
       return;
 
     case 's':
-      if (GET_CODE (x) == CONST_INT)
+      if (CONST_INT_P (x))
 	{
 	  HOST_WIDE_INT i = INTVAL (x);
 	  HOST_WIDE_INT s = exact_log2 (i & -i);
@@ -4691,7 +4691,7 @@ arc_print_operand (FILE *file, rtx x, int code)
 	  else
 	    fputs (reg_names[REGNO (x)+1], file);
 	}
-      else if (GET_CODE (x) == CONST_INT
+      else if (CONST_INT_P (x)
 	       || GET_CODE (x) == CONST_DOUBLE)
 	{
 	  rtx first, second, word;
@@ -5004,7 +5004,7 @@ arc_print_operand_address (FILE *file , rtx addr)
 	  }
 	gcc_assert (GET_CODE (c) == PLUS);
 	gcc_assert (GET_CODE (XEXP (c, 0)) == SYMBOL_REF);
-	gcc_assert (GET_CODE (XEXP (c, 1)) == CONST_INT);
+	gcc_assert (CONST_INT_P (XEXP (c, 1)));
 
 	output_address (VOIDmode, XEXP (addr, 0));
 
@@ -5861,7 +5861,7 @@ arc_rtx_costs (rtx x, machine_mode mode, int outer_code,
 	    }
 	  *total = COSTS_N_INSNS (1);
 	}
-      else if (GET_CODE (XEXP (x, 1)) != CONST_INT)
+      else if (!CONST_INT_P (XEXP (x, 1)))
 	*total = COSTS_N_INSNS (16);
       else
 	{
@@ -6014,7 +6014,7 @@ arc_legitimate_pic_addr_p (rtx addr)
 
   if (GET_CODE (addr) == PLUS)
     {
-      if (GET_CODE (XEXP (addr, 1)) != CONST_INT)
+      if (!CONST_INT_P (XEXP (addr, 1)))
 	return false;
       addr = XEXP (addr, 0);
     }
@@ -6306,13 +6306,13 @@ arc_output_pic_addr_const (FILE * file, rtx x, int code)
     case PLUS:
       /* FIXME: Not needed here.  */
       /* Some assemblers need integer constants to appear last (eg masm).  */
-      if (GET_CODE (XEXP (x, 0)) == CONST_INT)
+      if (CONST_INT_P (XEXP (x, 0)))
 	{
 	  arc_output_pic_addr_const (file, XEXP (x, 1), code);
 	  fprintf (file, "+");
 	  arc_output_pic_addr_const (file, XEXP (x, 0), code);
 	}
-      else if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+      else if (CONST_INT_P (XEXP (x, 1)))
 	{
 	  arc_output_pic_addr_const (file, XEXP (x, 0), code);
 	  if (INTVAL (XEXP (x, 1)) >= 0)
@@ -6332,7 +6332,7 @@ arc_output_pic_addr_const (FILE * file, rtx x, int code)
 
       arc_output_pic_addr_const (file, XEXP (x, 0), code);
       fprintf (file, "-");
-      if (GET_CODE (XEXP (x, 1)) == CONST_INT
+      if (CONST_INT_P (XEXP (x, 1))
 	  && INTVAL (XEXP (x, 1)) < 0)
 	{
 	  fprintf (file, "(");
@@ -6669,7 +6669,7 @@ arc_legitimate_address_p (machine_mode mode, rtx x, bool strict)
     return true;
   if (legitimate_small_data_address_p (x))
      return true;
-  if (GET_CODE (x) == CONST_INT && LARGE_INT (INTVAL (x)))
+  if (CONST_INT_P (x) && LARGE_INT (INTVAL (x)))
      return true;
 
   /* When we compile for size avoid const (@sym + offset)
@@ -10967,7 +10967,7 @@ compact_memory_operand_p (rtx op, machine_mode mode,
 	  && ((REGNO (plus0) >= FIRST_PSEUDO_REGISTER)
 	      || (COMPACT_GP_REG_P (REGNO (plus0)) && !av2short)
 	      || (IN_RANGE (REGNO (plus0), 0, 31) && av2short))
-	  && (GET_CODE (plus1) == CONST_INT))
+	  && (CONST_INT_P (plus1)))
 	{
 	  bool valid = false;
 
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
index 4a9dd07f558..377e29d3547 100644
--- a/gcc/config/arc/arc.h
+++ b/gcc/config/arc/arc.h
@@ -842,7 +842,7 @@ extern int arc_initial_elimination_offset(int from, int to);
 #define CONSTANT_ADDRESS_P(X)					\
   (flag_pic ? (arc_legitimate_pic_addr_p (X) || LABEL_P (X)):	\
    (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF	\
-    || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST))
+    || CONST_INT_P (X) || GET_CODE (X) == CONST))
 
 /* Is the argument a const_int rtx, containing an exact power of 2 */
 #define  IS_POWEROF2_P(X) (! ( (X) & ((X) - 1)) && (X))
diff --git a/gcc/config/arc/fpx.md b/gcc/config/arc/fpx.md
index 09c7b354715..0d0230baff0 100644
--- a/gcc/config/arc/fpx.md
+++ b/gcc/config/arc/fpx.md
@@ -239,7 +239,7 @@
   (use (match_dup 2))
   ]
   "TARGET_DPFP &&
-   !(GET_CODE(operands[2]) == CONST_DOUBLE && GET_CODE(operands[3]) == CONST_INT)"
+   !(GET_CODE(operands[2]) == CONST_DOUBLE && CONST_INT_P (operands[3]))"
   "@
      daddh%F0%F1 0,%H2,%L2
      daddh%F0%F1 0,%3,%L2"
@@ -263,7 +263,7 @@
   (use (match_dup 2))
   ]
   "TARGET_DPFP &&
-   !(GET_CODE(operands[2]) == CONST_DOUBLE && GET_CODE(operands[3]) == CONST_INT)"
+   !(GET_CODE(operands[2]) == CONST_DOUBLE && CONST_INT_P (operands[3]))"
   "@
     dmulh%F0%F1 0,%H2,%L2
     dmulh%F0%F1 0,%3, %L2"
@@ -294,8 +294,8 @@
   ; different USE pairs.
   (use (match_dup 2))]
   "TARGET_DPFP &&
-   !(GET_CODE(operands[2]) == CONST_DOUBLE && GET_CODE(operands[3]) == CONST_INT) &&
-   !(GET_CODE(operands[1]) == CONST_DOUBLE && GET_CODE(operands[3]) == CONST_INT)"
+   !(GET_CODE(operands[2]) == CONST_DOUBLE && CONST_INT_P (operands[3])) &&
+   !(GET_CODE(operands[1]) == CONST_DOUBLE && CONST_INT_P (operands[3]))"
   "@
      dsubh%F0%F1 0,%H2,%L2
      dsubh%F0%F1 0,%3,%L2
@@ -553,7 +553,7 @@
 		  (plus:DF (match_dup 1)
 			   (match_dup 2)))])]
  "TARGET_DPFP &&
-   !(GET_CODE(operands[2]) == CONST_DOUBLE && GET_CODE(operands[3]) == CONST_INT)"
+   !(GET_CODE(operands[2]) == CONST_DOUBLE && CONST_INT_P (operands[3]))"
  "@
     daddh%F0%F1 %H6, %H2, %L2
     daddh%F0%F1 %H6, %3, %L2"
@@ -576,7 +576,7 @@
 		  (mult:DF (match_dup 1)
 				      (match_dup 2)))])]
  "TARGET_DPFP &&
-   !(GET_CODE(operands[2]) == CONST_DOUBLE && GET_CODE(operands[3]) == CONST_INT)"
+   !(GET_CODE(operands[2]) == CONST_DOUBLE && CONST_INT_P (operands[3]))"
  "@
     dmulh%F0%F1 %H6, %H2, %L2
     dmulh%F0%F1 %H6, %3, %L2"
@@ -604,8 +604,8 @@
 		  (minus:DF (match_dup 1)
 				      (match_dup 2)))])]
  "TARGET_DPFP &&
-   !(GET_CODE(operands[2]) == CONST_DOUBLE && GET_CODE(operands[3]) == CONST_INT)  &&
-   !(GET_CODE(operands[1]) == CONST_DOUBLE && GET_CODE(operands[3]) == CONST_INT)"
+   !(GET_CODE(operands[2]) == CONST_DOUBLE && CONST_INT_P (operands[3]))  &&
+   !(GET_CODE(operands[1]) == CONST_DOUBLE && CONST_INT_P (operands[3]))"
  "@
   dsubh%F0%F1 %H6, %H2, %L2
   dsubh%F0%F1 %H6, %3, %L2
diff --git a/gcc/config/arc/predicates.md b/gcc/config/arc/predicates.md
index e0013b32f0f..0c2926dc5e1 100644
--- a/gcc/config/arc/predicates.md
+++ b/gcc/config/arc/predicates.md
@@ -222,7 +222,7 @@
       if ((GET_CODE (plus0) == REG)
 	  && ((REGNO (plus0) >= FIRST_PSEUDO_REGISTER)
 	      || COMPACT_GP_REG_P (REGNO (plus0)))
-	  && (GET_CODE (plus1) == CONST_INT))
+	  && (CONST_INT_P (plus1)))
 	{
 	  off = INTVAL (plus1);
 
@@ -244,7 +244,7 @@
       if ((GET_CODE (plus0) == REG)
 	  && ((REGNO (plus0) >= FIRST_PSEUDO_REGISTER)
 	      || SP_REG_P (REGNO (plus0)))
-	  && (GET_CODE (plus1) == CONST_INT))
+	  && (CONST_INT_P (plus1)))
 	{
 	  off = INTVAL (plus1);
 
diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c
index 319d7e2a035..dea2ee7cde5 100644
--- a/gcc/config/bfin/bfin.c
+++ b/gcc/config/bfin/bfin.c
@@ -190,7 +190,7 @@ legitimize_pic_address (rtx orig, rtx reg, rtx picreg)
 				     base == reg ? NULL_RTX : reg,
 				     picreg);
 
-      if (GET_CODE (addr) == CONST_INT)
+      if (CONST_INT_P (addr))
 	{
 	  gcc_assert (! reload_in_progress && ! reload_completed);
 	  addr = force_reg (Pmode, addr);
@@ -2743,7 +2743,7 @@ bfin_legitimate_address_p (machine_mode mode, rtx x, bool strict)
     if (REG_P (XEXP (x, 0))
 	&& bfin_valid_reg_p (REGNO (XEXP (x, 0)), strict, mode, PLUS)
 	&& ((GET_CODE (XEXP (x, 1)) == UNSPEC && mode == SImode)
-	    || (GET_CODE (XEXP (x, 1)) == CONST_INT
+	    || (CONST_INT_P (XEXP (x, 1))
 		&& bfin_valid_add (mode, INTVAL (XEXP (x, 1))))))
       return true;
     break;
@@ -2802,7 +2802,7 @@ bfin_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
   sym = XEXP (x, 0);
   x = XEXP (x, 1);
   if (GET_CODE (sym) != SYMBOL_REF
-      || GET_CODE (x) != CONST_INT)
+      || !CONST_INT_P (x))
     return true;
   offset = INTVAL (x);
 
@@ -2861,7 +2861,7 @@ bfin_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
       if (mode == SImode)
 	{
 	  if (GET_CODE (op0) == MULT
-	      && GET_CODE (XEXP (op0, 1)) == CONST_INT)
+	      && CONST_INT_P (XEXP (op0, 1)))
 	    {
 	      HOST_WIDE_INT val = INTVAL (XEXP (op0, 1));
 	      if (val == 2 || val == 4)
@@ -2886,7 +2886,7 @@ bfin_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
       else if (mode == DImode)
 	{
 	  *total = 6 * cost2;
-	  if (GET_CODE (op1) != CONST_INT
+	  if (!CONST_INT_P (op1)
 	      || !satisfies_constraint_Ks7 (op1))
 	    *total += rtx_cost (op1, mode, PLUS, 1, speed);
 	  if (GET_CODE (op0) != REG
@@ -2930,7 +2930,7 @@ bfin_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
 	  if ((GET_CODE (op0) == LSHIFTRT && GET_CODE (op1) == ASHIFT)
 	      || (GET_CODE (op0) == ASHIFT && GET_CODE (op1) == ZERO_EXTEND)
 	      || (GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
-	      || (GET_CODE (op0) == AND && GET_CODE (op1) == CONST_INT))
+	      || (GET_CODE (op0) == AND && CONST_INT_P (op1)))
 	    {
 	      *total = cost2;
 	      return true;
@@ -2967,7 +2967,7 @@ bfin_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
     case SIGN_EXTRACT:
       if (outer_code == SET
 	  && XEXP (x, 1) == const1_rtx
-	  && GET_CODE (XEXP (x, 2)) == CONST_INT)
+	  && CONST_INT_P (XEXP (x, 2)))
 	{
 	  *total = 2 * cost2;
 	  return true;
@@ -3051,7 +3051,7 @@ analyze_push_multiple_operation (rtx op)
       if (GET_CODE (dest) != PLUS
 	  || ! REG_P (XEXP (dest, 0))
 	  || REGNO (XEXP (dest, 0)) != REG_SP
-	  || GET_CODE (XEXP (dest, 1)) != CONST_INT
+	  || !CONST_INT_P (XEXP (dest, 1))
 	  || INTVAL (XEXP (dest, 1)) != -i * 4)
 	return 0;
 
@@ -3126,7 +3126,7 @@ analyze_pop_multiple_operation (rtx op)
       else if (GET_CODE (src) != PLUS
 	       || ! REG_P (XEXP (src, 0))
 	       || REGNO (XEXP (src, 0)) != REG_SP
-	       || GET_CODE (XEXP (src, 1)) != CONST_INT
+	       || !CONST_INT_P (XEXP (src, 1))
 	       || INTVAL (XEXP (src, 1)) != (i - 1) * 4)
 	return 0;
 
@@ -3230,9 +3230,9 @@ bfin_expand_cpymem (rtx dst, rtx src, rtx count_exp, rtx align_exp)
   HOST_WIDE_INT align = 0;
   unsigned HOST_WIDE_INT count = 0;
 
-  if (GET_CODE (align_exp) == CONST_INT)
+  if (CONST_INT_P (align_exp))
     align = INTVAL (align_exp);
-  if (GET_CODE (count_exp) == CONST_INT)
+  if (CONST_INT_P (count_exp))
     {
       count = INTVAL (count_exp);
 #if 0
@@ -4247,7 +4247,7 @@ harmless_null_pointer_p (rtx mem, int np_reg)
       && REG_P (XEXP (mem, 0)) && (int) REGNO (XEXP (mem, 0)) == np_reg)
     {
       mem = XEXP (mem, 1);
-      if (GET_CODE (mem) == CONST_INT && INTVAL (mem) > 0)
+      if (CONST_INT_P (mem) && INTVAL (mem) > 0)
 	return true;
     }
   return false;
diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md
index 6ac208d04a5..2adc3273901 100644
--- a/gcc/config/bfin/bfin.md
+++ b/gcc/config/bfin/bfin.md
@@ -828,14 +828,14 @@
   "reload_completed
    /* Always split symbolic operands; split integer constants that are
       too large for a single instruction.  */
-   && (GET_CODE (operands[1]) != CONST_INT
+   && (!CONST_INT_P (operands[1])
        || (INTVAL (operands[1]) < -32768
  	   || INTVAL (operands[1]) >= 65536
 	   || (INTVAL (operands[1]) >= 32768 && PREG_P (operands[0]))))"
   [(set (match_dup 0) (high:SI (match_dup 1)))
    (set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 1)))]
 {
-  if (GET_CODE (operands[1]) == CONST_INT
+  if (CONST_INT_P (operands[1])
       && split_load_immediate (operands))
     DONE;
   /* ??? Do something about TARGET_LOW_64K.  */
@@ -1092,7 +1092,7 @@
   xops[6] = gen_reg_rtx (SImode);
   xops[7] = gen_rtx_REG (BImode, REG_CC);
   if (!register_operand (xops[4], SImode)
-      && (GET_CODE (xops[4]) != CONST_INT
+      && (!CONST_INT_P (xops[4])
           || !satisfies_constraint_Ks7 (xops[4])))
     xops[4] = force_reg (SImode, xops[4]);
   if (!reg_overlap_mentioned_p (operands[0], operands[1])
@@ -1101,7 +1101,7 @@
   emit_insn (gen_add_with_carry (xops[0], xops[2], xops[4], xops[7]));
   emit_insn (gen_movbisi (xops[6], xops[7]));
   if (!register_operand (xops[5], SImode)
-      && (GET_CODE (xops[5]) != CONST_INT
+      && (!CONST_INT_P (xops[5])
           || !satisfies_constraint_Ks7 (xops[5])))
     xops[5] = force_reg (SImode, xops[5]);
   if (xops[5] != const0_rtx)
@@ -1640,7 +1640,7 @@
                    (match_operand:SI 2 "nonmemory_operand" "")))]
   ""
 {
- if (GET_CODE (operands[2]) == CONST_INT
+ if (CONST_INT_P (operands[2])
      && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
    {
      emit_insn (gen_movsi (operands[0], const0_rtx));
@@ -1689,7 +1689,7 @@
 		   (match_operand:SI 2 "const_int_operand" "")))]
   ""
 {
-  if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 16)
+  if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 16)
     FAIL;
 })
 
@@ -1699,7 +1699,7 @@
 		     (match_operand:SI 2 "const_int_operand" "")))]
   ""
 {
-  if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 16)
+  if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 16)
     FAIL;
   emit_insn (gen_rotl16 (operands[0], operands[1]));
   DONE;
diff --git a/gcc/config/bfin/predicates.md b/gcc/config/bfin/predicates.md
index adf89e17d0b..04eb584df0f 100644
--- a/gcc/config/bfin/predicates.md
+++ b/gcc/config/bfin/predicates.md
@@ -153,7 +153,7 @@
   return (REG_P (op1)
 	  && (REGNO (op1) == FRAME_POINTER_REGNUM
 	      || REGNO (op1) == STACK_POINTER_REGNUM)
-	  && GET_CODE (op2) == CONST_INT);
+	  && CONST_INT_P (op2));
 })
 
 ;; Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
@@ -164,7 +164,7 @@
 	    (match_test "GET_CODE (XEXP (op,0)) == PLUS
 			 && (GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
 			     || GET_CODE (XEXP (XEXP (op, 0), 0)) == LABEL_REF)
-			 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT"))))
+			 && CONST_INT_P (XEXP (XEXP (op, 0), 1))"))))
 
 ;; Returns 1 if OP is a plain constant or matched by symbolic_operand.
 (define_predicate "symbolic_or_const_operand"
diff --git a/gcc/config/c6x/c6x.c b/gcc/config/c6x/c6x.c
index f6c9bbfc674..62fab8376be 100644
--- a/gcc/config/c6x/c6x.c
+++ b/gcc/config/c6x/c6x.c
@@ -1346,7 +1346,7 @@ legitimize_pic_address (rtx orig, rtx reg, rtx picreg)
 				     base == reg ? NULL_RTX : reg,
 				     picreg);
 
-      if (GET_CODE (addr) == CONST_INT)
+      if (CONST_INT_P (addr))
 	{
 	  gcc_assert (! reload_in_progress && ! reload_completed);
 	  addr = force_reg (Pmode, addr);
@@ -2150,12 +2150,12 @@ c6x_print_operand (FILE *file, rtx x, int code)
       return;
 
     case 'k':
-      gcc_assert (GET_CODE (x) == CONST_INT);
+      gcc_assert (CONST_INT_P (x));
       v = INTVAL (x);
       fprintf (file, "%s", reg_names[v]);
       return;
     case 'K':
-      gcc_assert (GET_CODE (x) == CONST_INT);
+      gcc_assert (CONST_INT_P (x));
       v = INTVAL (x);
       gcc_assert ((v & 1) == 0);
       fprintf (file, "%s:%s", reg_names[v + 1], reg_names[v]);
@@ -2165,7 +2165,7 @@ c6x_print_operand (FILE *file, rtx x, int code)
     case 'S':
     case 'f':
     case 'F':
-      gcc_assert (GET_CODE (x) == CONST_INT);
+      gcc_assert (CONST_INT_P (x));
       v = INTVAL (x);
       for (i = 0; i < 32; i++)
 	{
@@ -2191,12 +2191,12 @@ c6x_print_operand (FILE *file, rtx x, int code)
       return;
 
     case 'n':
-      gcc_assert (GET_CODE (x) == CONST_INT);
+      gcc_assert (CONST_INT_P (x));
       output_addr_const (file, GEN_INT (-INTVAL (x)));
       return;
 
     case 'r':
-      gcc_assert (GET_CODE (x) == CONST_INT);
+      gcc_assert (CONST_INT_P (x));
       v = INTVAL (x);
       if (v < 0)
 	v = -v;
@@ -2204,7 +2204,7 @@ c6x_print_operand (FILE *file, rtx x, int code)
       return;
 
     case 'R':
-      gcc_assert (GET_CODE (x) == CONST_INT);
+      gcc_assert (CONST_INT_P (x));
       v = INTVAL (x);
       if (v < 0)
 	v = -v;
@@ -2212,7 +2212,7 @@ c6x_print_operand (FILE *file, rtx x, int code)
       return;
 
     case 'd':
-      gcc_assert (GET_CODE (x) == CONST_INT);
+      gcc_assert (CONST_INT_P (x));
       v = INTVAL (x);
       fputs (v == 2 ? "h" : v == 4 ? "w" : "d", file);
       return;
@@ -2232,7 +2232,7 @@ c6x_print_operand (FILE *file, rtx x, int code)
 	{
 	  x = XEXP (x, 0);
 	  gcc_assert (GET_CODE (x) == PLUS);
-	  gcc_assert (GET_CODE (XEXP (x, 1)) == CONST_INT);
+	  gcc_assert (CONST_INT_P (XEXP (x, 1)));
 	  v = INTVAL (XEXP (x, 1));
 	  x = XEXP (x, 0);
 
@@ -2432,7 +2432,7 @@ c6x_legitimate_address_p_1 (machine_mode mode, rtx x, bool strict,
 	  && (GET_CODE (XVECEXP (XEXP (x, 1), 0, 0)) == SYMBOL_REF
 	      || GET_CODE (XVECEXP (XEXP (x, 1), 0, 0)) == LABEL_REF))
 	return !no_large_offset;
-      if (GET_CODE (XEXP (x, 1)) != CONST_INT)
+      if (!CONST_INT_P (XEXP (x, 1)))
 	return false;
 
       off = INTVAL (XEXP (x, 1));
@@ -6010,7 +6010,7 @@ c6x_function_end (FILE *file, const char *fname)
 static bool
 shift_p (rtx x, enum rtx_code code, int amount)
 {
-  return (GET_CODE (x) == code && GET_CODE (XEXP (x, 1)) == CONST_INT
+  return (GET_CODE (x) == code && CONST_INT_P (XEXP (x, 1))
 	  && INTVAL (XEXP (x, 1)) == amount);
 }
 
@@ -6057,7 +6057,7 @@ c6x_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno, int *total,
 	  && GET_CODE (XEXP (x, 0)) == LSHIFTRT
 	  && GET_MODE (XEXP (x, 0)) == GET_MODE_2XWIDER_MODE (mode).require ()
 	  && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
-	  && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
+	  && CONST_INT_P (XEXP (XEXP (x, 0), 1))
 	  && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode))
 	{
 	  rtx mul = XEXP (XEXP (x, 0), 0);
@@ -6100,7 +6100,7 @@ c6x_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno, int *total,
       if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
 	  && INTEGRAL_MODE_P (mode)
 	  && GET_CODE (op0) == MULT
-	  && GET_CODE (XEXP (op0, 1)) == CONST_INT
+	  && CONST_INT_P (XEXP (op0, 1))
 	  && (INTVAL (XEXP (op0, 1)) == 2
 	      || INTVAL (XEXP (op0, 1)) == 4
 	      || (code == PLUS && INTVAL (XEXP (op0, 1)) == 8)))
@@ -6261,7 +6261,7 @@ static bool
 c6x_output_ttype (rtx x)
 {
   /* Use special relocations for symbol references.  */
-  if (GET_CODE (x) != CONST_INT)
+  if (!CONST_INT_P (x))
     fputs ("\t.ehtype\t", asm_out_file);
   else
     fputs ("\t.word\t", asm_out_file);
diff --git a/gcc/config/c6x/c6x.md b/gcc/config/c6x/c6x.md
index f9bf9ba99ab..56cd0c5e8d6 100644
--- a/gcc/config/c6x/c6x.md
+++ b/gcc/config/c6x/c6x.md
@@ -801,7 +801,7 @@
   rtx tmpreg = operands[2];
 
   if (GET_CODE (addr) == PLUS && XEXP (addr, 0) == stack_pointer_rtx
-      && GET_CODE (XEXP (addr, 1)) == CONST_INT)
+      && CONST_INT_P (XEXP (addr, 1)))
     {
       unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
       val &= GET_MODE_SIZE (<MODE>mode) - 1;
@@ -840,7 +840,7 @@
 		: operand_subword_force (operands[0], 0, DImode));
 
   if (GET_CODE (addr) == PLUS && XEXP (addr, 0) == stack_pointer_rtx
-      && GET_CODE (XEXP (addr, 1)) == CONST_INT)
+      && CONST_INT_P (XEXP (addr, 1)))
     {
       unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
       val &= GET_MODE_SIZE (<MODE>mode) - 1;
@@ -1293,8 +1293,8 @@
   rtx table = operands[3];
   rtx fail = operands[4];
 
-  gcc_assert (GET_CODE (operands[1]) == CONST_INT);
-  gcc_assert (GET_CODE (operands[2]) == CONST_INT);
+  gcc_assert (CONST_INT_P (operands[1]));
+  gcc_assert (CONST_INT_P (operands[2]));
 
   if (!reg_or_ucst4_operand (range, SImode))
     range = force_reg (SImode, range);
diff --git a/gcc/config/c6x/predicates.md b/gcc/config/c6x/predicates.md
index e625ae909d3..ea360f95543 100644
--- a/gcc/config/c6x/predicates.md
+++ b/gcc/config/c6x/predicates.md
@@ -86,7 +86,7 @@
 	    (match_test "GET_CODE (XEXP (op,0)) == PLUS
 			 && (GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
 			     || GET_CODE (XEXP (XEXP (op, 0), 0)) == LABEL_REF)
-			 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT"))))
+			 && CONST_INT_P (XEXP (XEXP (op, 0), 1))"))))
 
 (define_predicate "const_int_or_symbolic_operand"
   (ior (match_operand 0 "symbolic_operand")
@@ -188,7 +188,7 @@
       op = XEXP (op, 0);
       if (GET_CODE (op) != PLUS
 	  || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
-	  || GET_CODE (XEXP (op, 1)) != CONST_INT)
+	  || !CONST_INT_P (XEXP (op, 1)))
 	return false;
       offset = INTVAL (XEXP (op, 1));
       op = XEXP (op, 0);
diff --git a/gcc/config/cr16/cr16.c b/gcc/config/cr16/cr16.c
index 42b9e041fd0..9c9c4779eb2 100644
--- a/gcc/config/cr16/cr16.c
+++ b/gcc/config/cr16/cr16.c
@@ -68,12 +68,12 @@
 
 /* Nonzero if the rtx X is a signed const int of n bits.  */
 #define RTX_SIGNED_INT_FITS_N_BITS(X, n)                \
-  ((GET_CODE (X) == CONST_INT                          \
+  ((CONST_INT_P (X)                          \
    && SIGNED_INT_FITS_N_BITS (INTVAL (X), n)) ? 1 : 0)
 
 /* Nonzero if the rtx X is an unsigned const int of n bits.  */
 #define RTX_UNSIGNED_INT_FITS_N_BITS(X, n)               \
-  ((GET_CODE (X) == CONST_INT                            \
+  ((CONST_INT_P (X)                            \
    && UNSIGNED_INT_FITS_N_BITS (INTVAL (X), n)) ? 1 : 0)
 
 /* Structure for stack computations.  */
@@ -783,9 +783,9 @@ cr16_decompose_const (rtx x, int *code, enum data_model_type *data,
     case PLUS:
     case MINUS:
       /* Look into the tree nodes.  */
-      if (GET_CODE (XEXP (x, 0)) == CONST_INT)
+      if (CONST_INT_P (XEXP (x, 0)))
 	cr16_decompose_const (XEXP (x, 1), code, data, treat_as_const);
-      else if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+      else if (CONST_INT_P (XEXP (x, 1)))
 	cr16_decompose_const (XEXP (x, 0), code, data, treat_as_const);
       return;
     default:
@@ -1106,7 +1106,7 @@ cr16_decompose_address (rtx addr, struct cr16_address *out,
 	      return CR16_INVALID;
 	    }
 	  /* Now check if the operand 1 of operand 0 is const_int.  */
-	  if (GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
+	  if (CONST_INT_P (XEXP (XEXP (addr, 0), 1)))
 	    {
 	      disp = XEXP (XEXP (addr, 0), 1);
 	      if (debug_print)
@@ -1164,7 +1164,7 @@ legitimate_pic_operand_p (rtx x)
       if (GET_CODE (XEXP (x, 0)) == PLUS
 	  && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
 	      || GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF)
-	  && (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
+	  && (CONST_INT_P (XEXP (XEXP (x, 0), 1))))
 	return 0;
       break;
     case MEM:
diff --git a/gcc/config/cr16/cr16.h b/gcc/config/cr16/cr16.h
index ae528ca80cc..91e96ba67b3 100644
--- a/gcc/config/cr16/cr16.h
+++ b/gcc/config/cr16/cr16.h
@@ -340,11 +340,11 @@ enum reg_class
 
 /* This check is for sbit/cbit instruction.  */
 #define OK_FOR_Z(OP) \
-  ((GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == CONST_INT) \
+  ((GET_CODE (OP) == MEM && CONST_INT_P (XEXP (OP, 0))) \
    || (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG) \
    || (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == PLUS \
        && GET_CODE (XEXP ((XEXP (OP, 0)), 0)) == REG \
-       && GET_CODE (XEXP ((XEXP (OP, 0)), 1)) == CONST_INT))
+       && CONST_INT_P (XEXP ((XEXP (OP, 0)), 1))))
 
 /* Stack layout and calling conventions.  */
 #define STACK_GROWS_DOWNWARD 1
@@ -417,7 +417,7 @@ struct cumulative_args
   (GET_CODE (X) == LABEL_REF        \
    || GET_CODE (X) == SYMBOL_REF    \
    || GET_CODE (X) == CONST         \
-   || GET_CODE (X) == CONST_INT)
+   || CONST_INT_P (X))
 
 #define MAX_REGS_PER_ADDRESS    2
 
diff --git a/gcc/config/cr16/cr16.md b/gcc/config/cr16/cr16.md
index 1df9e38f0e8..6f87c734151 100644
--- a/gcc/config/cr16/cr16.md
+++ b/gcc/config/cr16/cr16.md
@@ -414,14 +414,14 @@
 			 (match_operand:QI 2 "nonmemory_operand" "")))]
   ""
   {
-    if (GET_CODE (operands[2]) == CONST_INT)
+    if (CONST_INT_P (operands[2]))
       {
 	/* If the constant is not in range, try placing it in a reg */
 	if (!UNSIGNED_INT_FITS_N_BITS(INTVAL (operands[2]),<shImmBits>))
 	operands[2] = copy_to_mode_reg(QImode, operands[2]);
       }
 
-    if (GET_CODE (operands[2]) != CONST_INT)
+    if (!CONST_INT_P (operands[2]))
       operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
   }
 )
@@ -486,14 +486,14 @@
 			 (match_operand:QI 2 "reg_or_int_operand" "")))]
   ""
   {
-    if (GET_CODE (operands[2]) == CONST_INT)
+    if (CONST_INT_P (operands[2]))
       {
 	/* If the constant is not in range, try placing it in a reg */
 	if (!UNSIGNED_INT_FITS_N_BITS(INTVAL (operands[2]),<shImmBits>))
 	operands[2] = copy_to_mode_reg(QImode, operands[2]);
       }
 
-	if (GET_CODE (operands[2]) != CONST_INT)
+	if (!CONST_INT_P (operands[2]))
 	operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
    }
 )
@@ -935,7 +935,7 @@
    (clobber (match_operand:SI 2 "register_operand" "+r"))]
   "flag_pic == FAR_PIC"
   {
-    if (GET_CODE (operands[0]) != CONST_INT)
+    if (!CONST_INT_P (operands[0]))
       return "loadd\t%g0, %2 \n\tjal %2";
     else
       return "jal %2";
@@ -955,7 +955,7 @@
        perform checks on const_int code addresses as it
        assumes all const_int are data addresses.
     */
-    if (GET_CODE (operands[0]) != CONST_INT)
+    if (!CONST_INT_P (operands[0]))
       return "bal (ra), %a0";
     else
       operands[4] = GEN_INT ((INTVAL (operands[0]))>>1);
@@ -1010,7 +1010,7 @@
    (clobber (match_operand:SI 3 "register_operand" "+r"))]
   "flag_pic == FAR_PIC"
   {
-    if (GET_CODE (operands[1]) != CONST_INT)
+    if (!CONST_INT_P (operands[1]))
       return "loadd\t%g1, %3 \n\tjal %3";
     else
       return "jal %3";
@@ -1031,7 +1031,7 @@
        perform checks on const_int code addresses as it
        assumes all const_int are data addresses.
     */
-    if (GET_CODE (operands[1]) != CONST_INT) 
+    if (!CONST_INT_P (operands[1])) 
       return "bal (ra), %a1";
     else
       {
diff --git a/gcc/config/cr16/predicates.md b/gcc/config/cr16/predicates.md
index 7336f6d1be1..755ad8fca5e 100644
--- a/gcc/config/cr16/predicates.md
+++ b/gcc/config/cr16/predicates.md
@@ -117,7 +117,7 @@
 (define_predicate "call_imm_operand"
   (match_operand 0 "immediate_operand")
 {
-  if (GET_CODE (op) != CONST_INT) return 1;
+  if (!CONST_INT_P (op)) return 1;
     return (UNSIGNED_INT_FITS_N_BITS(INTVAL (op), 24)) ? 1 : 0;
 })
 
diff --git a/gcc/config/cris/cris.md b/gcc/config/cris/cris.md
index 23c760c1a4d..12421bf2c3b 100644
--- a/gcc/config/cris/cris.md
+++ b/gcc/config/cris/cris.md
@@ -1453,7 +1453,7 @@
   if (GET_CODE (indreg) == POST_INC)
     indreg = XEXP (indreg, 0);
   if (!REG_P (indreg)
-      || GET_CODE (operands[2]) != CONST_INT
+      || !CONST_INT_P (operands[2])
       || !REG_P (operands[0])
       || REGNO (operands[0]) != 0
       || INTVAL (operands[2]) > CRIS_SP_REGNUM
@@ -1481,7 +1481,7 @@
   if (GET_CODE (indreg) == POST_INC)
     indreg = XEXP (indreg, 0);
   if (!REG_P (indreg)
-      || GET_CODE (operands[2]) != CONST_INT
+      || !CONST_INT_P (operands[2])
       || !REG_P (operands[1])
       || REGNO (operands[1]) != 0
       || INTVAL (operands[2]) > CRIS_SP_REGNUM
@@ -3442,7 +3442,7 @@
 		  (match_operand:SI 2 "nonmemory_operand" "r,i")))]
   "TARGET_V32"
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     {
       /* Constant operands are zero-extended, so only 32-bit operands
 	 may be negative.  */
diff --git a/gcc/config/csky/csky.c b/gcc/config/csky/csky.c
index 3cfa13e22cd..5e8b14e7665 100644
--- a/gcc/config/csky/csky.c
+++ b/gcc/config/csky/csky.c
@@ -3325,7 +3325,7 @@ csky_print_operand_address (FILE *stream,
 
   decompose_csky_address (x, &addr);
 
-  if (addr.label && addr.disp && GET_CODE (addr.disp) == CONST_INT)
+  if (addr.label && addr.disp && CONST_INT_P (addr.disp))
     {
       fprintf (stream, "[");
       csky_output_constpool_label (stream, addr.label);
@@ -3337,7 +3337,7 @@ csky_print_operand_address (FILE *stream,
       csky_output_constpool_label (stream, addr.label);
       fprintf (stream, "]");
     }
-  else if (addr.symbol && addr.disp && GET_CODE (addr.disp) == CONST_INT)
+  else if (addr.symbol && addr.disp && CONST_INT_P (addr.disp))
     {
       fprintf (stream, "[");
       output_addr_const (stream, addr.symbol);
@@ -3349,7 +3349,7 @@ csky_print_operand_address (FILE *stream,
       output_addr_const (stream, addr.symbol);
       fprintf (stream, "]");
     }
-  else if (addr.disp && GET_CODE (addr.disp) == CONST_INT)
+  else if (addr.disp && CONST_INT_P (addr.disp))
     fprintf (stream, "(%s, %d)",
 	     reg_names[REGNO (addr.base)], (int) INTVAL (addr.disp));
   else if (addr.disp && GET_CODE (addr.disp) == UNSPEC)
@@ -4012,7 +4012,7 @@ csky_output_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
 	      }
 	}
       /* The situation mov integer to reg.  */
-      else if (GET_CODE (src) == CONST_INT ||
+      else if (CONST_INT_P (src) ||
 	       (GET_CODE (src) == CONST_DOUBLE && GET_MODE (src) == SFmode))
 	{
 	  HOST_WIDE_INT x, y;
@@ -4127,7 +4127,7 @@ csky_output_ck801_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
 		gcc_unreachable ();
 	      }
 	}
-      else if (GET_CODE (src) == CONST_INT)
+      else if (CONST_INT_P (src))
 	{
 	  if (REGNO (dst) > 7)
 	    return "lrw\t%0, %x1\t";
@@ -4290,7 +4290,7 @@ csky_output_movedouble (rtx operands[],
 	  else
 	    return "ld.w\t%0, %1\n\tld.w\t%R0, %R1";
 	}
-      else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE)
+      else if (CONST_INT_P (src) || GET_CODE (src) == CONST_DOUBLE)
 	{
 	  split_double (src, operands + 2, operands + 3);
 
@@ -4416,7 +4416,7 @@ csky_output_ck801_movedouble (rtx operands[],
 	  else
 	    return "ld.w\t%0, %1\n\tld.w\t%R0, %R1";
 	}
-      else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE)
+      else if (CONST_INT_P (src) || GET_CODE (src) == CONST_DOUBLE)
 	{
 	  split_double (src, operands + 2, operands + 3);
 
@@ -4733,7 +4733,7 @@ csky_symbolic_address_p (rtx x)
       x = XEXP (x, 0);
       return ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
 	       || GET_CODE (XEXP (x, 0)) == LABEL_REF)
-	      && GET_CODE (XEXP (x, 1)) == CONST_INT);
+	      && CONST_INT_P (XEXP (x, 1)));
     default:
       return 0;
     }
@@ -4749,7 +4749,7 @@ csky_emit_compare (enum rtx_code code, rtx op0, rtx op1)
   bool invert;
   rtx cc_reg = gen_rtx_REG (CCmode, CSKY_CC_REGNUM);
 
-  if (GET_CODE (op1) == CONST_INT)
+  if (CONST_INT_P (op1))
     {
       HOST_WIDE_INT val = INTVAL (op1);
 
@@ -4787,7 +4787,7 @@ csky_emit_compare (enum rtx_code code, rtx op0, rtx op1)
 	}
     }
 
-  if (CONSTANT_P (op1) && GET_CODE (op1) != CONST_INT)
+  if (CONSTANT_P (op1) && !CONST_INT_P (op1))
     op1 = force_reg (GET_MODE (op1), op1);
 
   /* cmpnei: 0-31 (K immediate)
@@ -4802,7 +4802,7 @@ csky_emit_compare (enum rtx_code code, rtx op0, rtx op1)
       /* Fall through.  */
       /* Use normal condition, cmpne.  */
       case NE:
-	if (GET_CODE (op1) == CONST_INT
+	if (CONST_INT_P (op1)
 	    && (TARGET_MINI_REGISTERS
 		? !csky_literal_K_operand (op1, SImode)
 		: !csky_literal_I_operand (op1, SImode)))
@@ -4816,7 +4816,7 @@ csky_emit_compare (enum rtx_code code, rtx op0, rtx op1)
       /* Fall through.  */
       /* Use normal condition, reversed cmplt.  */
       case GT:
-	if (GET_CODE (op1) == CONST_INT)
+	if (CONST_INT_P (op1))
 	  op1 = force_reg (SImode, op1);
       break;
 
@@ -4828,7 +4828,7 @@ csky_emit_compare (enum rtx_code code, rtx op0, rtx op1)
       /* Use normal condition, cmplt.  */
       case LT:
 	/* covered by btsti x,31.  */
-	if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0
+	if (CONST_INT_P (op1) && INTVAL (op1) != 0
 	    && (TARGET_MINI_REGISTERS
 		? !csky_literal_J_operand (op1, SImode)
 		: !csky_literal_Uk_operand (op1, SImode)))
@@ -4838,13 +4838,13 @@ csky_emit_compare (enum rtx_code code, rtx op0, rtx op1)
       /* Use inverted condition, cmple.  */
       case GTU:
 	/* We coped with unsigned > 0 above.  */
-	gcc_assert (GET_CODE (op1) != CONST_INT || INTVAL (op1) != 0);
+	gcc_assert (!CONST_INT_P (op1) || INTVAL (op1) != 0);
 	code = LEU;
 	invert = true;
       /* Fall through.  */
       /* Use normal condition, reversed cmphs.  */
       case LEU:
-	if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0)
+	if (CONST_INT_P (op1) && INTVAL (op1) != 0)
 	  op1 = force_reg (SImode, op1);
 	break;
 
@@ -4855,7 +4855,7 @@ csky_emit_compare (enum rtx_code code, rtx op0, rtx op1)
       /* Fall through.  */
       /* Use normal condition, cmphs.  */
       case GEU:
-	if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0
+	if (CONST_INT_P (op1) && INTVAL (op1) != 0
 	    && (TARGET_MINI_REGISTERS
 		? !csky_literal_J_operand (op1, SImode)
 		: !csky_literal_Uk_operand (op1, SImode)))
@@ -5774,7 +5774,7 @@ csky_legitimize_pic_address (rtx orig, rtx reg, bool gotrel_p)
       offset = csky_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
 					    base == reg ? 0 : reg, gotrel_p);
 
-      if (GET_CODE (offset) == CONST_INT)
+      if (CONST_INT_P (offset))
 	return plus_constant (Pmode, base, INTVAL (offset));
 
       return gen_rtx_PLUS (Pmode, base, offset);
diff --git a/gcc/config/csky/csky.md b/gcc/config/csky/csky.md
index 13c33e205f3..7a8b382c1d8 100644
--- a/gcc/config/csky/csky.md
+++ b/gcc/config/csky/csky.md
@@ -262,7 +262,7 @@
     if (GET_CODE (operands[0]) == MEM)
 	operands[1] = force_reg (HImode, operands[1]);
     else if (CONSTANT_P (operands[1])
-	     && (GET_CODE (operands[1]) != CONST_INT
+	     && (!CONST_INT_P (operands[1])
 		 || (! CSKY_CONST_OK_FOR_I (INTVAL (operands[1]))
 		     && ! CSKY_CONST_OK_FOR_Ub (INTVAL (operands[1]))
 		     && ! CSKY_CONST_OK_FOR_Uc (INTVAL (operands[1]))))
@@ -303,7 +303,7 @@
     if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM)
 	operands[1] = force_reg (QImode, operands[1]);
     else if (CONSTANT_P (operands[1])
-	     && (GET_CODE (operands[1]) != CONST_INT
+	     && (!CONST_INT_P (operands[1])
 		 || (! CSKY_CONST_OK_FOR_I (INTVAL (operands[1]))
 		     && ! CSKY_CONST_OK_FOR_Ub (INTVAL (operands[1]))
 		     && ! CSKY_CONST_OK_FOR_Uc (INTVAL (operands[1]))))
@@ -2054,7 +2054,7 @@
     int regno, count, i;
     rtx base,src;
 
-    if (GET_CODE (operands[2]) != CONST_INT
+    if (!CONST_INT_P (operands[2])
 	|| INTVAL (operands[2]) < 2
 	|| INTVAL (operands[2]) > CSKY_MAX_MULTIPLE_STLD
 	|| GET_CODE (operands[1]) != MEM
@@ -2092,7 +2092,7 @@
 
     /* Support only storing a constant number of registers to memory and
        only if at least two registers. */
-    if (GET_CODE (operands[2]) != CONST_INT
+    if (!CONST_INT_P (operands[2])
 	|| INTVAL (operands[2]) < 2
 	|| INTVAL (operands[2]) > CSKY_MAX_MULTIPLE_STLD
 	|| GET_CODE (operands[0]) != MEM
diff --git a/gcc/config/csky/predicates.md b/gcc/config/csky/predicates.md
index 7e0f8d04a0a..0c67e4e9cbf 100644
--- a/gcc/config/csky/predicates.md
+++ b/gcc/config/csky/predicates.md
@@ -52,7 +52,7 @@
 	  || GET_MODE (SET_SRC (elt)) != SImode
 	  || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
 	  || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
-	  || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
+	  || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt), 0), 1))
 	  || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
 	return 0;
     }
@@ -93,7 +93,7 @@
 	  || GET_MODE (SET_DEST (elt)) != SImode
 	  || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
 	  || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
-	  || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
+	  || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt), 0), 1))
 	  || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
 	return 0;
     }
@@ -175,7 +175,7 @@
   {
     if (register_operand (op, mode))
       return 1;
-    if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
+    if (CONST_INT_P (op) && INTVAL (op) == 0)
       return 1;
     return 0;
   })
diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c
index 5ac092583ba..d38867e4227 100644
--- a/gcc/config/darwin.c
+++ b/gcc/config/darwin.c
@@ -759,7 +759,7 @@ machopic_indirect_data_reference (rtx orig, rtx reg)
       base = machopic_indirect_data_reference (XEXP (orig, 0), reg);
       orig = machopic_indirect_data_reference (XEXP (orig, 1),
 					       (base == reg ? 0 : reg));
-      if (MACHOPIC_INDIRECT && (GET_CODE (orig) == CONST_INT))
+      if (MACHOPIC_INDIRECT && (CONST_INT_P (orig)))
 	result = plus_constant (Pmode, base, INTVAL (orig));
       else
 	result = gen_rtx_PLUS (Pmode, base, orig);
@@ -1036,7 +1036,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
       base = machopic_legitimize_pic_address (XEXP (orig, 0), Pmode, reg);
       orig = machopic_legitimize_pic_address (XEXP (orig, 1),
 					      Pmode, (base == reg ? 0 : reg));
-      if (GET_CODE (orig) == CONST_INT)
+      if (CONST_INT_P (orig))
 	{
 	  pic_ref = plus_constant (Pmode, base, INTVAL (orig));
 	  is_complex = 1;
@@ -1750,19 +1750,19 @@ machopic_select_rtx_section (machine_mode mode, rtx x,
 			     unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
 {
   if (GET_MODE_SIZE (mode) == 8
-      && (GET_CODE (x) == CONST_INT
+      && (CONST_INT_P (x)
 	  || GET_CODE (x) == CONST_WIDE_INT
 	  || GET_CODE (x) == CONST_DOUBLE))
     return darwin_sections[literal8_section];
   else if (GET_MODE_SIZE (mode) == 4
-	   && (GET_CODE (x) == CONST_INT
+	   && (CONST_INT_P (x)
 	       || GET_CODE (x) == CONST_WIDE_INT
 	       || GET_CODE (x) == CONST_DOUBLE))
     return darwin_sections[literal4_section];
   else if (HAVE_GAS_LITERAL16
 	   && TARGET_64BIT
 	   && GET_MODE_SIZE (mode) == 16
-	   && (GET_CODE (x) == CONST_INT
+	   && (CONST_INT_P (x)
 	       || GET_CODE (x) == CONST_WIDE_INT
 	       || GET_CODE (x) == CONST_DOUBLE
 	       || GET_CODE (x) == CONST_VECTOR))
diff --git a/gcc/config/epiphany/epiphany.c b/gcc/config/epiphany/epiphany.c
index 657a8886ac7..11f188f13e0 100644
--- a/gcc/config/epiphany/epiphany.c
+++ b/gcc/config/epiphany/epiphany.c
@@ -1411,9 +1411,9 @@ epiphany_print_operand_address (FILE *file, machine_mode /*mode*/, rtx addr)
 	}
       break;
     case PLUS :
-      if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
+      if (CONST_INT_P (XEXP (addr, 0)))
 	offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
-      else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
+      else if (CONST_INT_P (XEXP (addr, 1)))
 	offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
       else
 	base = XEXP (addr, 0), index = XEXP (addr, 1);
diff --git a/gcc/config/epiphany/epiphany.h b/gcc/config/epiphany/epiphany.h
index 8ebdbfe42f2..38f6cac5a59 100644
--- a/gcc/config/epiphany/epiphany.h
+++ b/gcc/config/epiphany/epiphany.h
@@ -603,14 +603,14 @@ typedef struct GTY (()) machine_function
 /* Recognize any constant value that is a valid address.  */
 #define CONSTANT_ADDRESS_P(X) \
 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF	\
- || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST)
+ || CONST_INT_P (X) || GET_CODE (X) == CONST)
 
 #define RTX_OK_FOR_OFFSET_P(MODE, X) \
   RTX_OK_FOR_OFFSET_1 (GET_MODE_CLASS (MODE) == MODE_VECTOR_INT \
 		       && epiphany_vect_align == 4 \
 		       ? (machine_mode) SImode : (machine_mode) (MODE), X)
 #define RTX_OK_FOR_OFFSET_1(MODE, X) \
-  (GET_CODE (X) == CONST_INT \
+  (CONST_INT_P (X) \
    && !(INTVAL (X) & (GET_MODE_SIZE (MODE) - 1)) \
    && INTVAL (X) >= -2047 * (int) GET_MODE_SIZE (MODE) \
    && INTVAL (X) <=  2047 * (int) GET_MODE_SIZE (MODE))
diff --git a/gcc/config/fr30/fr30.c b/gcc/config/fr30/fr30.c
index d21fc45e3f1..54e5766241f 100644
--- a/gcc/config/fr30/fr30.c
+++ b/gcc/config/fr30/fr30.c
@@ -579,7 +579,7 @@ fr30_print_operand (FILE *file, rtx x, int code)
 
     case 'A':
       /* Print a signed byte value as an unsigned value.  */
-      if (GET_CODE (x) != CONST_INT)
+      if (!CONST_INT_P (x))
 	output_operand_lossage ("fr30_print_operand: invalid operand to %%A code");
       else
 	{
@@ -594,7 +594,7 @@ fr30_print_operand (FILE *file, rtx x, int code)
       return;
       
     case 'x':
-      if (GET_CODE (x) != CONST_INT
+      if (!CONST_INT_P (x)
 	  || INTVAL (x) < 16
 	  || INTVAL (x) > 32)
 	output_operand_lossage ("fr30_print_operand: invalid %%x code");
@@ -645,7 +645,7 @@ fr30_print_operand (FILE *file, rtx x, int code)
 	  if (GET_CODE (XEXP (x0, 0)) != REG
 	      || REGNO (XEXP (x0, 0)) < FRAME_POINTER_REGNUM
 	      || REGNO (XEXP (x0, 0)) > STACK_POINTER_REGNUM
-	      || GET_CODE (XEXP (x0, 1)) != CONST_INT)
+	      || !CONST_INT_P (XEXP (x0, 1)))
 	    {
 	      fprintf (stderr, "bad INDEXed address:");
 	      debug_rtx (x);
diff --git a/gcc/config/fr30/fr30.h b/gcc/config/fr30/fr30.h
index bfcaa49d812..85cd49a2ed1 100644
--- a/gcc/config/fr30/fr30.h
+++ b/gcc/config/fr30/fr30.h
@@ -558,14 +558,14 @@ enum reg_class
 	  && ((MODE) == SImode || (MODE) == SFmode)			\
 	  && GET_CODE (XEXP (X, 0)) == REG				\
           && REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM		\
-	  && GET_CODE (XEXP (X, 1)) == CONST_INT			\
+	  && CONST_INT_P (XEXP (X, 1))			\
 	  && IN_RANGE (INTVAL (XEXP (X, 1)), 0, (1 <<  6) - 4))		\
 	goto LABEL;							\
       if (GET_CODE (X) == PLUS						\
 	  && ((MODE) == SImode || (MODE) == SFmode)			\
 	  && GET_CODE (XEXP (X, 0)) == REG				\
           && REGNO (XEXP (X, 0)) == FRAME_POINTER_REGNUM		\
-	  && GET_CODE (XEXP (X, 1)) == CONST_INT			\
+	  && CONST_INT_P (XEXP (X, 1))			\
 	  && IN_RANGE (INTVAL (XEXP (X, 1)), -(1 << 9), (1 <<  9) - 4))	\
         goto LABEL;							\
     }									\
@@ -580,7 +580,7 @@ enum reg_class
 	  && ((MODE) == SImode || (MODE) == SFmode)			\
 	  && GET_CODE (XEXP (X, 0)) == REG				\
           && REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM		\
-	  && GET_CODE (XEXP (X, 1)) == CONST_INT			\
+	  && CONST_INT_P (XEXP (X, 1))			\
 	  && IN_RANGE (INTVAL (XEXP (X, 1)), 0, (1 <<  6) - 4))		\
 	goto LABEL;							\
       if (GET_CODE (X) == PLUS						\
@@ -588,7 +588,7 @@ enum reg_class
 	  && GET_CODE (XEXP (X, 0)) == REG				\
           && (REGNO (XEXP (X, 0)) == FRAME_POINTER_REGNUM		\
 	      || REGNO (XEXP (X, 0)) == ARG_POINTER_REGNUM)		\
-	  && GET_CODE (XEXP (X, 1)) == CONST_INT			\
+	  && CONST_INT_P (XEXP (X, 1))			\
 	  && IN_RANGE (INTVAL (XEXP (X, 1)), -(1 << 9), (1 <<  9) - 4))	\
         goto LABEL;							\
     }									\
diff --git a/gcc/config/fr30/fr30.md b/gcc/config/fr30/fr30.md
index dcdf6dd1e97..5a369cfa249 100644
--- a/gcc/config/fr30/fr30.md
+++ b/gcc/config/fr30/fr30.md
@@ -656,7 +656,7 @@
   if (   GET_CODE (operands[2]) == REG
       || GET_CODE (operands[2]) == SUBREG)
     emit_insn (gen_addsi_regs (operands[0], operands[1], operands[2]));
-  else if (GET_CODE (operands[2]) != CONST_INT)
+  else if (!CONST_INT_P (operands[2]))
     emit_insn (gen_addsi_big_int (operands[0], operands[1], operands[2]));
   else if (INTVAL (operands[2]) >= -16
 	   && INTVAL (operands[2]) <= 15
diff --git a/gcc/config/fr30/predicates.md b/gcc/config/fr30/predicates.md
index 1fb58d1298a..20873856906 100644
--- a/gcc/config/fr30/predicates.md
+++ b/gcc/config/fr30/predicates.md
@@ -24,7 +24,7 @@
   (match_code "const_int")
 {
   return
-    (GET_CODE (op) == CONST_INT
+    (CONST_INT_P (op)
      && INTVAL (op) >= -512
      && INTVAL (op) <=  508
      && ((INTVAL (op) & 3) == 0));
@@ -117,7 +117,7 @@
 {
   return
     (GET_CODE (op) == REG
-     || (GET_CODE (op) == CONST_INT
+     || (CONST_INT_P (op)
 	 && INTVAL (op) >= -16
 	 && INTVAL (op) <=  15));
 })
diff --git a/gcc/config/frv/frv.c b/gcc/config/frv/frv.c
index f0c9351f083..bccd1efa58a 100644
--- a/gcc/config/frv/frv.c
+++ b/gcc/config/frv/frv.c
@@ -569,7 +569,7 @@ frv_const_unspec_p (rtx x, struct frv_unspec *unspec)
     {
       unspec->offset = 0;
       x = XEXP (x, 0);
-      if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
+      if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
 	{
 	  unspec->offset += INTVAL (XEXP (x, 1));
 	  x = XEXP (x, 0);
@@ -2190,7 +2190,7 @@ frv_expand_block_move (rtx operands[])
   rtx orig_src	= operands[1];
   rtx bytes_rtx	= operands[2];
   rtx align_rtx = operands[3];
-  int constp	= (GET_CODE (bytes_rtx) == CONST_INT);
+  int constp	= (CONST_INT_P (bytes_rtx));
   int align;
   int bytes;
   int offset;
@@ -2212,7 +2212,7 @@ frv_expand_block_move (rtx operands[])
     return FALSE;
 
   /* This should be a fixed size alignment.  */
-  gcc_assert (GET_CODE (align_rtx) == CONST_INT);
+  gcc_assert (CONST_INT_P (align_rtx));
 
   align = INTVAL (align_rtx);
 
@@ -2288,7 +2288,7 @@ frv_expand_block_clear (rtx operands[])
   rtx orig_dest = operands[0];
   rtx bytes_rtx	= operands[1];
   rtx align_rtx = operands[3];
-  int constp	= (GET_CODE (bytes_rtx) == CONST_INT);
+  int constp	= (CONST_INT_P (bytes_rtx));
   int align;
   int bytes;
   int offset;
@@ -2303,7 +2303,7 @@ frv_expand_block_clear (rtx operands[])
     return FALSE;
 
   /* This should be a fixed size alignment.  */
-  gcc_assert (GET_CODE (align_rtx) == CONST_INT);
+  gcc_assert (CONST_INT_P (align_rtx));
 
   align = INTVAL (align_rtx);
 
@@ -2540,7 +2540,7 @@ frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
     case PLUS:
       x0 = XEXP (x, 0);
       x1 = XEXP (x, 1);
-      if (GET_CODE (x0) == CONST_INT)
+      if (CONST_INT_P (x0))
 	{
 	  x0 = XEXP (x, 1);
 	  x1 = XEXP (x, 0);
@@ -2557,7 +2557,7 @@ frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
     {
       if (!x1)
 	x1 = const0_rtx;
-      else if (GET_CODE (x1) != CONST_INT)
+      else if (!CONST_INT_P (x1))
 	fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
     }
 
@@ -2735,7 +2735,7 @@ frv_print_operand (FILE * file, rtx x, int code)
   if (code != 0 && !ISALPHA (code))
     value = 0;
 
-  else if (GET_CODE (x) == CONST_INT)
+  else if (CONST_INT_P (x))
     value = INTVAL (x);
 
   else if (GET_CODE (x) == CONST_DOUBLE)
@@ -2850,7 +2850,7 @@ frv_print_operand (FILE * file, rtx x, int code)
 
     case 'g':
       /* Print appropriate GOT function.  */
-      if (GET_CODE (x) != CONST_INT)
+      if (!CONST_INT_P (x))
 	fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x);
       fputs (unspec_got_name (INTVAL (x)), file);
       break;
@@ -2881,15 +2881,15 @@ frv_print_operand (FILE * file, rtx x, int code)
     case 'i':
       /* For jump instructions, print 'i' if the operand is a constant or
          is an expression that adds a constant.  */
-      if (GET_CODE (x) == CONST_INT)
+      if (CONST_INT_P (x))
         fputs ("i", file);
 
       else
         {
-          if (GET_CODE (x) == CONST_INT
+          if (CONST_INT_P (x)
               || (GET_CODE (x) == PLUS
-                  && (GET_CODE (XEXP (x, 1)) == CONST_INT
-                      || GET_CODE (XEXP (x, 0)) == CONST_INT)))
+                  && (CONST_INT_P (XEXP (x, 1))
+                      || CONST_INT_P (XEXP (x, 0)))))
             fputs ("i", file);
         }
       break;
@@ -2950,7 +2950,7 @@ frv_print_operand (FILE * file, rtx x, int code)
 
     case 'P':
       /* Print PIC label using operand as the number.  */
-      if (GET_CODE (x) != CONST_INT)
+      if (!CONST_INT_P (x))
 	fatal_insn ("bad insn to frv_print_operand, P modifier:", x);
 
       fprintf (file, ".LCF%ld", (long)INTVAL (x));
@@ -2964,7 +2964,7 @@ frv_print_operand (FILE * file, rtx x, int code)
 
     case 'z':
       /* If value is 0, print gr0, otherwise it must be a register.  */
-      if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
+      if (CONST_INT_P (x) && INTVAL (x) == 0)
 	fputs (reg_names[GPR_R0], file);
 
       else if (GET_CODE (x) == REG)
@@ -2976,7 +2976,7 @@ frv_print_operand (FILE * file, rtx x, int code)
 
     case 'x':
       /* Print constant in hex.  */
-      if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
+      if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
         {
 	  fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
 	  break;
@@ -2988,7 +2988,7 @@ frv_print_operand (FILE * file, rtx x, int code)
       if (GET_CODE (x) == REG)
         fputs (reg_names [REGNO (x)], file);
 
-      else if (GET_CODE (x) == CONST_INT
+      else if (CONST_INT_P (x)
               || GET_CODE (x) == CONST_DOUBLE)
         fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
 
@@ -4042,7 +4042,7 @@ frv_emit_movsi (rtx dest, rtx src)
 	  sym = XEXP (sym, 0);
 	  if (GET_CODE (sym) == PLUS
 	      && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF
-	      && GET_CODE (XEXP (sym, 1)) == CONST_INT)
+	      && CONST_INT_P (XEXP (sym, 1)))
 	    sym = XEXP (sym, 0);
 	  if (GET_CODE (sym) == SYMBOL_REF)
 	    goto handle_sym;
@@ -4252,13 +4252,13 @@ output_move_single (rtx operands[], rtx insn)
 		}
 	    }
 
-	  else if (GET_CODE (src) == CONST_INT
+	  else if (CONST_INT_P (src)
 		   || GET_CODE (src) == CONST_DOUBLE)
 	    {
 	      /* gpr <- integer/floating constant */
 	      HOST_WIDE_INT value;
 
-	      if (GET_CODE (src) == CONST_INT)
+	      if (CONST_INT_P (src))
 		value = INTVAL (src);
 
 	      else if (mode == SFmode)
@@ -4458,7 +4458,7 @@ output_move_double (rtx operands[], rtx insn)
 	      return "#";
 	    }
 
-	  else if (GET_CODE (src) == CONST_INT
+	  else if (CONST_INT_P (src)
 		   || GET_CODE (src) == CONST_DOUBLE)
 	    return "#";
 	}
@@ -4828,7 +4828,7 @@ frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
 		   (clobber (<ccr_reg>))])  */
 
   /* Handle various cases of conditional move involving two constants.  */
-  if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
+  if (CONST_INT_P (src1) && CONST_INT_P (src2))
     {
       HOST_WIDE_INT value1 = INTVAL (src1);
       HOST_WIDE_INT value2 = INTVAL (src2);
@@ -4859,10 +4859,10 @@ frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
      register.  */
   else
     {
-      if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
+      if (CONST_INT_P (src1) && INTVAL (src1) != 0)
 	src1 = force_reg (GET_MODE (dest), src1);
 
-      if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
+      if (CONST_INT_P (src2) && INTVAL (src2) != 0)
 	src2 = force_reg (GET_MODE (dest), src2);
     }
 
@@ -4907,7 +4907,7 @@ frv_split_cond_move (rtx operands[])
 					  const0_rtx)));
 
   /* Handle various cases of conditional move involving two constants.  */
-  if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
+  if (CONST_INT_P (src1) && CONST_INT_P (src2))
     {
       HOST_WIDE_INT value1 = INTVAL (src1);
       HOST_WIDE_INT value2 = INTVAL (src2);
@@ -5074,7 +5074,7 @@ frv_split_minmax (rtx operands[])
 
   /* If are taking the min/max of a nonzero constant, load that first, and
      then do a conditional move of the other value.  */
-  if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
+  if (CONST_INT_P (src2) && INTVAL (src2) != 0)
     {
       gcc_assert (!rtx_equal_p (dest, src1));
 
@@ -5731,7 +5731,7 @@ frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
 
   if (dump_file)
     {
-      if (GET_CODE (value) == CONST_INT)
+      if (CONST_INT_P (value))
 	fprintf (dump_file, "Register %s will hold %ld\n",
 		 reg_names[ REGNO (reg)], (long)INTVAL (value));
 
@@ -5936,7 +5936,7 @@ frv_ifcvt_modify_insn (ce_if_block *ce_info,
 	{
 	  op0 = XEXP (src, 0);
 	  op1 = XEXP (src, 1);
-	  if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
+	  if (GET_CODE (op0) == SIGN_EXTEND && CONST_INT_P (op1))
 	    {
 	      op1 = frv_ifcvt_load_value (op1, insn);
 	      if (op1)
@@ -8516,7 +8516,7 @@ frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
     if ((i & ACC_MASK) == i)
       global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1;
 
-  if (GET_CODE (opval) != CONST_INT)
+  if (!CONST_INT_P (opval))
     {
       error ("accumulator is not a constant integer");
       return NULL_RTX;
@@ -8569,7 +8569,7 @@ frv_matching_accg_mode (machine_mode mode)
 static rtx
 frv_io_address_cookie (rtx address)
 {
-  return (GET_CODE (address) == CONST_INT
+  return (CONST_INT_P (address)
 	  ? GEN_INT (INTVAL (address) / 8 * 8)
 	  : const0_rtx);
 }
@@ -8605,7 +8605,7 @@ frv_read_iacc_argument (machine_mode mode, tree call,
   rtx op;
 
   op = frv_read_argument (call, index);
-  if (GET_CODE (op) != CONST_INT
+  if (!CONST_INT_P (op)
       || INTVAL (op) < 0
       || INTVAL (op) > IACC_LAST - IACC_FIRST
       || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0)
@@ -8631,7 +8631,7 @@ frv_read_iacc_argument (machine_mode mode, tree call,
 static int
 frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval)
 {
-  if (GET_CODE (opval) != CONST_INT)
+  if (!CONST_INT_P (opval))
     {
       error ("%qs expects a constant argument", insn_data[icode].name);
       return FALSE;
@@ -8764,7 +8764,7 @@ frv_expand_cut_builtin (enum insn_code icode, tree call, rtx target)
   if (! op0)
     return NULL_RTX;
 
-  if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
+  if (icode == CODE_FOR_mdcutssi || CONST_INT_P (op1))
     {
       if (! frv_check_constant_argument (icode, 2, op1))
     	return NULL_RTX;
diff --git a/gcc/config/frv/frv.h b/gcc/config/frv/frv.h
index 501515ca263..219153368ae 100644
--- a/gcc/config/frv/frv.h
+++ b/gcc/config/frv/frv.h
@@ -1470,9 +1470,9 @@ __asm__("\n"								\
    define this macro if all constants (including `SYMBOL_REF') can be immediate
    operands when generating position independent code.  */
 #define LEGITIMATE_PIC_OPERAND_P(X)					\
-  (   GET_CODE (X) == CONST_INT						\
+  (   CONST_INT_P (X)						\
    || GET_CODE (X) == CONST_DOUBLE					\
-   || (GET_CODE (X) == HIGH && GET_CODE (XEXP (X, 0)) == CONST_INT)	\
+   || (GET_CODE (X) == HIGH && CONST_INT_P (XEXP (X, 0)))	\
    || got12_operand (X, VOIDmode))					\
 
 
diff --git a/gcc/config/frv/frv.md b/gcc/config/frv/frv.md
index 6e8db59fdd9..b33c272075a 100644
--- a/gcc/config/frv/frv.md
+++ b/gcc/config/frv/frv.md
@@ -2707,7 +2707,7 @@
   ""
   "
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     {
       emit_insn (gen_mulsidi3_const (operands[0], operands[1], operands[2]));
       DONE;
@@ -2740,7 +2740,7 @@
   ""
   "
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     {
       emit_insn (gen_umulsidi3_const (operands[0], operands[1], operands[2]));
       DONE;
@@ -5304,9 +5304,9 @@
   rtx reg2;
   rtx reg3;
 
-  gcc_assert (GET_CODE (operands[1]) == CONST_INT);
+  gcc_assert (CONST_INT_P (operands[1]));
 
-  gcc_assert (GET_CODE (operands[2]) == CONST_INT);
+  gcc_assert (CONST_INT_P (operands[2]));
 
   /* If we can't generate an immediate instruction, promote to register.  */
   if (! IN_RANGE (INTVAL (range), -2048, 2047))
diff --git a/gcc/config/frv/predicates.md b/gcc/config/frv/predicates.md
index d89c759da3a..02e5ce97789 100644
--- a/gcc/config/frv/predicates.md
+++ b/gcc/config/frv/predicates.md
@@ -109,7 +109,7 @@
 (define_predicate "gpr_or_int12_operand"
   (match_code "reg,subreg,const_int,const")
 {
-  if (GET_CODE (op) == CONST_INT)
+  if (CONST_INT_P (op))
     return IN_RANGE (INTVAL (op), -2048, 2047);
 
   if (got12_operand (op, mode))
@@ -140,7 +140,7 @@
 {
   int regno;
 
-  if (GET_CODE (op) == CONST_INT)
+  if (CONST_INT_P (op))
     return IN_RANGE (INTVAL (op), -2048, 2047);
 
   if (GET_MODE (op) != mode && mode != VOIDmode)
@@ -169,7 +169,7 @@
 (define_predicate "gpr_or_int10_operand"
   (match_code "reg,subreg,const_int")
 {
-  if (GET_CODE (op) == CONST_INT)
+  if (CONST_INT_P (op))
     return IN_RANGE (INTVAL (op), -512, 511);
 
   if (GET_MODE (op) != mode && mode != VOIDmode)
@@ -194,7 +194,7 @@
 (define_predicate "gpr_or_int_operand"
   (match_code "reg,subreg,const_int")
 {
-  if (GET_CODE (op) == CONST_INT)
+  if (CONST_INT_P (op))
     return TRUE;
 
   if (GET_MODE (op) != mode && mode != VOIDmode)
@@ -469,7 +469,7 @@
   if (!integer_register_operand (XEXP (addr, 0), Pmode))
     return FALSE;
 
-  if (GET_CODE (XEXP (addr, 1)) != CONST_INT)
+  if (!CONST_INT_P (XEXP (addr, 1)))
     return FALSE;
 
   return TRUE;
@@ -490,7 +490,7 @@
 (define_predicate "int12_operand"
   (match_code "const_int")
 {
-  if (GET_CODE (op) != CONST_INT)
+  if (!CONST_INT_P (op))
     return FALSE;
 
   return IN_RANGE (INTVAL (op), -2048, 2047);
@@ -522,7 +522,7 @@
 	return FALSE;
 
       op = XEXP (op, 0);
-      if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
+      if (GET_CODE (op) == PLUS && CONST_INT_P (XEXP (op, 1)))
 	op = XEXP (op, 0);
       return GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF;
 
@@ -1025,7 +1025,7 @@
       if (got12_operand (addr1, VOIDmode))
 	return TRUE;
 
-      if (GET_CODE (addr1) != CONST_INT)
+      if (!CONST_INT_P (addr1))
 	return FALSE;
 
       if ((INTVAL (addr1) & 7) != 0)
@@ -1066,7 +1066,7 @@
 (define_predicate "call_operand"
   (match_code "reg,subreg,const_int,const,symbol_ref")
 {
-  if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT)
+  if (GET_MODE (op) != mode && mode != VOIDmode && !CONST_INT_P (op))
     return FALSE;
 
   if (GET_CODE (op) == SYMBOL_REF)
@@ -1085,7 +1085,7 @@
 (define_predicate "sibcall_operand"
   (match_code "reg,subreg,const_int,const")
 {
-  if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT)
+  if (GET_MODE (op) != mode && mode != VOIDmode && !CONST_INT_P (op))
     return FALSE;
 
   /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
@@ -1101,7 +1101,7 @@
 (define_predicate "upper_int16_operand"
   (match_code "const_int")
 {
-  if (GET_CODE (op) != CONST_INT)
+  if (!CONST_INT_P (op))
     return FALSE;
 
   return ((INTVAL (op) & 0xffff) == 0);
@@ -1112,7 +1112,7 @@
 (define_predicate "uint16_operand"
   (match_code "const_int")
 {
-  if (GET_CODE (op) != CONST_INT)
+  if (!CONST_INT_P (op))
     return FALSE;
 
   return IN_RANGE (INTVAL (op), 0, 0xffff);
@@ -1131,7 +1131,7 @@
       return GET_MODE (op) == SImode
 	&& GET_CODE (XEXP (op, 0)) == PLUS
 	&& GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
-	&& GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT;
+	&& CONST_INT_P (XEXP (XEXP (op, 0), 1));
     }
 
   return c == SYMBOL_REF || c == CONST_INT;
@@ -1441,7 +1441,7 @@
 (define_predicate "fpr_or_int6_operand"
   (match_code "reg,subreg,const_int")
 {
-  if (GET_CODE (op) == CONST_INT)
+  if (CONST_INT_P (op))
     return IN_RANGE (INTVAL (op), -32, 31);
 
   if (GET_MODE (op) != mode && mode != VOIDmode)
@@ -1466,7 +1466,7 @@
 (define_predicate "int6_operand"
   (match_code "const_int")
 {
-  if (GET_CODE (op) != CONST_INT)
+  if (!CONST_INT_P (op))
     return FALSE;
 
   return IN_RANGE (INTVAL (op), -32, 31);
@@ -1477,7 +1477,7 @@
 (define_predicate "int5_operand"
   (match_code "const_int")
 {
-  return GET_CODE (op) == CONST_INT && IN_RANGE (INTVAL (op), -16, 15);
+  return CONST_INT_P (op) && IN_RANGE (INTVAL (op), -16, 15);
 })
 
 ;; Return 1 if operand is a 5-bit unsigned immediate.
@@ -1485,7 +1485,7 @@
 (define_predicate "uint5_operand"
   (match_code "const_int")
 {
-  return GET_CODE (op) == CONST_INT && IN_RANGE (INTVAL (op), 0, 31);
+  return CONST_INT_P (op) && IN_RANGE (INTVAL (op), 0, 31);
 })
 
 ;; Return 1 if operand is a 4-bit unsigned immediate.
@@ -1493,7 +1493,7 @@
 (define_predicate "uint4_operand"
   (match_code "const_int")
 {
-  return GET_CODE (op) == CONST_INT && IN_RANGE (INTVAL (op), 0, 15);
+  return CONST_INT_P (op) && IN_RANGE (INTVAL (op), 0, 15);
 })
 
 ;; Return 1 if operand is a 1-bit unsigned immediate (0 or 1).
@@ -1501,7 +1501,7 @@
 (define_predicate "uint1_operand"
   (match_code "const_int")
 {
-  return GET_CODE (op) == CONST_INT && IN_RANGE (INTVAL (op), 0, 1);
+  return CONST_INT_P (op) && IN_RANGE (INTVAL (op), 0, 1);
 })
 
 ;; Return 1 if operand is a valid ACC register number.
diff --git a/gcc/config/ft32/constraints.md b/gcc/config/ft32/constraints.md
index cb72132d600..6f2d49b3d4d 100644
--- a/gcc/config/ft32/constraints.md
+++ b/gcc/config/ft32/constraints.md
@@ -28,14 +28,14 @@
        (match_test "(!ft32_is_mem_pm(op))")
        (ior (match_test "GET_CODE (XEXP (op, 0)) == SYMBOL_REF")
             (match_test "GET_CODE (XEXP (op, 0)) == LABEL_REF")
-            (match_test "GET_CODE (XEXP (op, 0)) == CONST_INT")
+            (match_test "CONST_INT_P (XEXP (op, 0))")
             (and (match_test "(GET_CODE (XEXP (op, 0)) == PLUS)")
                  (ior (match_test "GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF")
                       (match_test "GET_CODE (XEXP (XEXP (op, 0), 0)) == LABEL_REF")
-                      (match_test "GET_CODE (XEXP (XEXP (op, 0), 0)) == CONST_INT"))
+                      (match_test "CONST_INT_P (XEXP (XEXP (op, 0), 0))"))
                  (ior (match_test "GET_CODE (XEXP (XEXP (op, 0), 1)) == SYMBOL_REF")
                       (match_test "GET_CODE (XEXP (XEXP (op, 0), 1)) == LABEL_REF")
-                      (match_test "GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT"))))))
+                      (match_test "CONST_INT_P (XEXP (XEXP (op, 0), 1))"))))))
 
 (define_memory_constraint "B"
   "An offset address."
@@ -56,7 +56,7 @@
        (match_test "ft32_is_mem_pm(op) && (
           (GET_CODE (XEXP (op, 0)) == SYMBOL_REF) ||
           (GET_CODE (XEXP (op, 0)) == LABEL_REF) ||
-          (GET_CODE (XEXP (op, 0)) == CONST_INT) ||
+          (CONST_INT_P (XEXP (op, 0))) ||
           (GET_CODE (XEXP (op, 0)) == CONST))"
        )))
 
diff --git a/gcc/config/ft32/predicates.md b/gcc/config/ft32/predicates.md
index a3178a1f5b5..89cf0b587b9 100644
--- a/gcc/config/ft32/predicates.md
+++ b/gcc/config/ft32/predicates.md
@@ -39,7 +39,7 @@
   if (MEM_P (op)
       && GET_CODE (XEXP (op, 0)) == PLUS
       && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
-      && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
+      && CONST_INT_P (XEXP (XEXP (op, 0), 1)))
     return 1;
 
   return general_operand (op, mode);
diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index 66b822962ae..b8ecd299cc0 100644
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -2640,12 +2640,12 @@
    (match_operand:SI 2 "")]
   ""
   {
-    if (GET_CODE (operands[1]) != CONST_INT
-	|| GET_CODE (operands[2]) != CONST_INT)
+    if (!CONST_INT_P (operands[1])
+	|| !CONST_INT_P (operands[2]))
       {
 	rtx _0_1_2_3 = gen_rtx_REG (V64SImode, VGPR_REGNO (1));
 	rtx tmp = _0_1_2_3;
-	if (GET_CODE (operands[1]) != CONST_INT
+	if (!CONST_INT_P (operands[1])
 	    || INTVAL (operands[1]) != 0)
 	  {
 	    tmp = gen_reg_rtx (V64SImode);
diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c
index 7df22c8286f..674eed31bc3 100644
--- a/gcc/config/gcn/gcn.c
+++ b/gcc/config/gcn/gcn.c
@@ -824,7 +824,7 @@ gcn_fp_constant_p (rtx x, bool allow_vector)
 bool
 gcn_inline_constant_p (rtx x)
 {
-  if (GET_CODE (x) == CONST_INT)
+  if (CONST_INT_P (x))
     return INTVAL (x) >= -16 && INTVAL (x) < 64;
   if (GET_CODE (x) == CONST_DOUBLE)
     return gcn_inline_fp_constant_p (x, false);
@@ -903,7 +903,7 @@ gcn_inline_constant64_p (rtx x)
       return true;
     }
 
-  if (GET_CODE (x) != CONST_INT)
+  if (!CONST_INT_P (x))
     return false;
 
   rtx val_lo = gcn_operand_part (DImode, x, 0);
@@ -921,7 +921,7 @@ gcn_constant64_p (rtx x)
   if (!gcn_constant_p (x))
     return false;
 
-  if (GET_CODE (x) != CONST_INT)
+  if (!CONST_INT_P (x))
     return true;
 
   /* Negative numbers are only allowed if they can be encoded within src0,
@@ -1228,7 +1228,7 @@ gcn_addr_space_legitimate_address_p (machine_mode mode, rtx x, bool strict,
 		|| gcn_address_register_p (x1, SImode, strict))
 	      return true;
 	    else*/
-	    if (GET_CODE (x1) == CONST_INT)
+	    if (CONST_INT_P (x1))
 	      {
 		if (INTVAL (x1) >= 0 && INTVAL (x1) < (1 << 20)
 		    /* The low bits of the offset are ignored, even when
@@ -1265,7 +1265,7 @@ gcn_addr_space_legitimate_address_p (machine_mode mode, rtx x, bool strict,
 		  : !gcn_vec_address_register_p (x, DImode, strict))
 		return false;
 
-	      if (GET_CODE (x1) == CONST_INT)
+	      if (CONST_INT_P (x1))
 		{
 		  if (INTVAL (x1) >= 0 && INTVAL (x1) < (1 << 12)
 		      /* The low bits of the offset are ignored, even when
@@ -1290,7 +1290,7 @@ gcn_addr_space_legitimate_address_p (machine_mode mode, rtx x, bool strict,
 	  rtx base = XEXP (x, 0);
 	  rtx offset = XEXP (x, 1);
 
-	  bool immediate_p = (GET_CODE (offset) == CONST_INT
+	  bool immediate_p = (CONST_INT_P (offset)
 			      /* Signed 13-bit immediate.  */
 			      && INTVAL (offset) >= -(1 << 12)
 			      && INTVAL (offset) < (1 << 12)
@@ -1353,7 +1353,7 @@ gcn_addr_space_legitimate_address_p (machine_mode mode, rtx x, bool strict,
 		return false;
 	    }
 	  else if (GET_CODE (x1) == CONST_VECTOR
-		   && GET_CODE (CONST_VECTOR_ELT (x1, 0)) == CONST_INT
+		   && CONST_INT_P (CONST_VECTOR_ELT (x1, 0))
 		   && single_cst_vector_p (x1))
 	    {
 	      x1 = CONST_VECTOR_ELT (x1, 0);
@@ -5245,7 +5245,7 @@ print_operand_address (FILE *file, rtx mem)
 	reg = XEXP (addr, 0);
 	offset = XEXP (addr, 1);
 	print_reg (file, reg);
-	if (GET_CODE (offset) == CONST_INT)
+	if (CONST_INT_P (offset))
 	  fprintf (file, " offset:" HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
 	else
 	  abort ();
@@ -5354,7 +5354,7 @@ print_operand_address (FILE *file, rtx mem)
 	fprintf (file, ", ");
 	if (GET_CODE (offset) == REG)
 	  print_reg (file, reg);
-	else if (GET_CODE (offset) == CONST_INT)
+	else if (CONST_INT_P (offset))
 	  fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
 	else
 	  abort ();
@@ -5678,7 +5678,7 @@ print_operand (FILE *file, rtx x, int code)
 	rtx val = XEXP (x0, 1);
 	if (GET_CODE (val) == CONST_VECTOR)
 	  val = CONST_VECTOR_ELT (val, 0);
-	if (GET_CODE (val) != CONST_INT)
+	if (!CONST_INT_P (val))
 	  {
 	    output_operand_lossage ("invalid %%xn code");
 	    return;
diff --git a/gcc/config/gcn/gcn.md b/gcc/config/gcn/gcn.md
index bbd2db29515..f4c8e8d1251 100644
--- a/gcc/config/gcn/gcn.md
+++ b/gcc/config/gcn/gcn.md
@@ -583,7 +583,7 @@
   global_store_dwordx2\t%A0, %1%O0%g0"
   "(reload_completed && !MEM_P (operands[0]) && !MEM_P (operands[1])
     && !gcn_sgpr_move_p (operands[0], operands[1]))
-   || (GET_CODE (operands[1]) == CONST_INT && !gcn_constant64_p (operands[1]))"
+   || (CONST_INT_P (operands[1]) && !gcn_constant64_p (operands[1]))"
   [(set (match_dup 0) (match_dup 1))
    (set (match_dup 2) (match_dup 3))]
   {
@@ -635,7 +635,7 @@
   ds_read_b128\t%0, %A1%O1\;s_waitcnt\tlgkmcnt(0)"
   "reload_completed
    && REG_P (operands[0])
-   && (REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_INT)"
+   && (REG_P (operands[1]) || CONST_INT_P (operands[1]))"
   [(set (match_dup 0) (match_dup 1))
    (set (match_dup 2) (match_dup 3))
    (set (match_dup 4) (match_dup 5))
diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c
index b68ee395a07..d64eda8a5e0 100644
--- a/gcc/config/h8300/h8300.c
+++ b/gcc/config/h8300/h8300.c
@@ -730,7 +730,7 @@ h8300_stack_offset_p (rtx x, int offset)
 
   return (GET_CODE (x) == PLUS
 	  && XEXP (x, 0) == stack_pointer_rtx
-	  && GET_CODE (XEXP (x, 1)) == CONST_INT
+	  && CONST_INT_P (XEXP (x, 1))
 	  && INTVAL (XEXP (x, 1)) == offset);
 }
 
@@ -1502,7 +1502,7 @@ h8300_print_operand (FILE *file, rtx x, int code)
 	}
       break;
     case 'G':
-      gcc_assert (GET_CODE (x) == CONST_INT);
+      gcc_assert (CONST_INT_P (x));
       fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
       break;
     case 'S':
@@ -1631,7 +1631,7 @@ h8300_print_operand (FILE *file, rtx x, int code)
       fputs (cond_string (reverse_condition (GET_CODE (x))), file);
       break;
     case 'm':
-      gcc_assert (GET_CODE (x) == CONST_INT);
+      gcc_assert (CONST_INT_P (x));
       switch (INTVAL (x))
 	{
 	case 1:
@@ -1654,39 +1654,39 @@ h8300_print_operand (FILE *file, rtx x, int code)
       h8300_print_operand_address (file, VOIDmode, x);
       break;
     case 's':
-      if (GET_CODE (x) == CONST_INT)
+      if (CONST_INT_P (x))
 	fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
       else
 	fprintf (file, "%s", byte_reg (x, 0));
       break;
     case 't':
-      if (GET_CODE (x) == CONST_INT)
+      if (CONST_INT_P (x))
 	fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
       else
 	fprintf (file, "%s", byte_reg (x, 1));
       break;
     case 'w':
-      if (GET_CODE (x) == CONST_INT)
+      if (CONST_INT_P (x))
 	fprintf (file, "#%ld", INTVAL (x) & 0xff);
       else
 	fprintf (file, "%s",
 		 byte_reg (x, TARGET_H8300 ? 2 : 0));
       break;
     case 'x':
-      if (GET_CODE (x) == CONST_INT)
+      if (CONST_INT_P (x))
 	fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
       else
 	fprintf (file, "%s",
 		 byte_reg (x, TARGET_H8300 ? 3 : 1));
       break;
     case 'y':
-      if (GET_CODE (x) == CONST_INT)
+      if (CONST_INT_P (x))
 	fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
       else
 	fprintf (file, "%s", byte_reg (x, 0));
       break;
     case 'z':
-      if (GET_CODE (x) == CONST_INT)
+      if (CONST_INT_P (x))
 	fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
       else
 	fprintf (file, "%s", byte_reg (x, 1));
@@ -2155,7 +2155,7 @@ h8300_get_index (rtx x, machine_mode mode, int *size)
 	  rtx index;
 
 	  if (GET_CODE (x) == AND
-	      && GET_CODE (XEXP (x, 1)) == CONST_INT
+	      && CONST_INT_P (XEXP (x, 1))
 	      && (factor == 0
 		  || INTVAL (XEXP (x, 1)) == 0xff * factor
 		  || INTVAL (XEXP (x, 1)) == 0xffff * factor))
@@ -2170,7 +2170,7 @@ h8300_get_index (rtx x, machine_mode mode, int *size)
 	    }
 
 	  if (GET_CODE (index) == MULT
-	      && GET_CODE (XEXP (index, 1)) == CONST_INT
+	      && CONST_INT_P (XEXP (index, 1))
 	      && (factor == 0 || factor == INTVAL (XEXP (index, 1))))
 	    return XEXP (index, 0);
 	}
@@ -2260,7 +2260,7 @@ static unsigned int
 h8300_constant_length (rtx constant)
 {
   /* Check for (@d:16,Reg).  */
-  if (GET_CODE (constant) == CONST_INT
+  if (CONST_INT_P (constant)
       && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff))
     return 2;
 
@@ -2285,7 +2285,7 @@ h8300_displacement_length (rtx addr, int size)
 
   /* Check for @(d:2,Reg).  */
   if (register_operand (XEXP (addr, 0), VOIDmode)
-      && GET_CODE (offset) == CONST_INT
+      && CONST_INT_P (offset)
       && (INTVAL (offset) == size
 	  || INTVAL (offset) == size * 2
 	  || INTVAL (offset) == size * 3))
@@ -2318,7 +2318,7 @@ h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass)
 	 will fit into a 16-bit immediate field.  */
       if (TARGET_H8300SX
 	  && size == 4
-	  && GET_CODE (op) == CONST_INT
+	  && CONST_INT_P (op)
 	  && IN_RANGE (INTVAL (op), 0, 0xffff))
 	return 2;
 
@@ -2682,7 +2682,7 @@ h8sx_emit_movmd (rtx dest, rtx src, rtx length,
   if (!flag_omit_frame_pointer && optimize_size)
     return false;
 
-  if (GET_CODE (length) == CONST_INT)
+  if (CONST_INT_P (length))
     {
       rtx dest_reg, src_reg, first_dest, first_src;
       HOST_WIDE_INT n;
@@ -2843,7 +2843,7 @@ compute_mov_length (rtx *operands)
 	      if (REG_P (src))
 		return 4;
 
-	      if (GET_CODE (src) == CONST_INT)
+	      if (CONST_INT_P (src))
 		{
 		  if (src == const0_rtx)
 		    return 4;
@@ -2954,7 +2954,7 @@ compute_mov_length (rtx *operands)
 		    return 2;
 		}
 
-	      if (GET_CODE (src) == CONST_INT)
+	      if (CONST_INT_P (src))
 		{
 		  int val = INTVAL (src);
 
@@ -3020,7 +3020,7 @@ compute_mov_length (rtx *operands)
 	 longest.  */
       if (GET_CODE (addr) == PLUS
 	  && GET_CODE (XEXP (addr, 0)) == REG
-	  && GET_CODE (XEXP (addr, 1)) == CONST_INT
+	  && CONST_INT_P (XEXP (addr, 1))
 	  && INTVAL (XEXP (addr, 1)) > -32768
 	  && INTVAL (XEXP (addr, 1)) < 32767)
 	return base_length - 4;
@@ -3051,7 +3051,7 @@ output_plussi (rtx *operands)
       if (GET_CODE (operands[2]) == REG)
 	return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
 
-      if (GET_CODE (operands[2]) == CONST_INT)
+      if (CONST_INT_P (operands[2]))
 	{
 	  HOST_WIDE_INT n = INTVAL (operands[2]);
 
@@ -3067,7 +3067,7 @@ output_plussi (rtx *operands)
     }
   else
     {
-      if (GET_CODE (operands[2]) == CONST_INT
+      if (CONST_INT_P (operands[2])
 	  && register_operand (operands[1], VOIDmode))
 	{
 	  HOST_WIDE_INT intval = INTVAL (operands[2]);
@@ -3110,7 +3110,7 @@ output_plussi (rtx *operands)
 	    }
 	}
 
-      if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
+      if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
 	{
 	  operands[2] = GEN_INT (-INTVAL (operands[2]));
 	  return "sub.l\t%S2,%S0";
@@ -3135,7 +3135,7 @@ compute_plussi_length (rtx *operands)
       if (GET_CODE (operands[2]) == REG)
 	return 6;
 
-      if (GET_CODE (operands[2]) == CONST_INT)
+      if (CONST_INT_P (operands[2]))
 	{
 	  HOST_WIDE_INT n = INTVAL (operands[2]);
 
@@ -3151,7 +3151,7 @@ compute_plussi_length (rtx *operands)
     }
   else
     {
-      if (GET_CODE (operands[2]) == CONST_INT
+      if (CONST_INT_P (operands[2])
 	  && register_operand (operands[1], VOIDmode))
 	{
 	  HOST_WIDE_INT intval = INTVAL (operands[2]);
@@ -3189,7 +3189,7 @@ compute_plussi_length (rtx *operands)
 	    return 4;
 	}
 
-      if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
+      if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
 	return h8300_length_from_table (operands[0],
 					GEN_INT (-INTVAL (operands[2])),
 					&addl_length_table);
@@ -3215,7 +3215,7 @@ compute_plussi_cc (rtx *operands)
     }
   else
     {
-      if (GET_CODE (operands[2]) == CONST_INT
+      if (CONST_INT_P (operands[2])
 	  && register_operand (operands[1], VOIDmode))
 	{
 	  HOST_WIDE_INT intval = INTVAL (operands[2]);
@@ -3266,7 +3266,7 @@ output_logical_op (machine_mode mode, rtx *operands)
   enum rtx_code code = GET_CODE (operands[3]);
   /* Pretend that every byte is affected if both operands are registers.  */
   const unsigned HOST_WIDE_INT intval =
-    (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
+    (unsigned HOST_WIDE_INT) ((CONST_INT_P (operands[2]))
 			      /* Always use the full instruction if the
 				 first operand is in memory.  It is better
 				 to use define_splits to generate the shorter
@@ -3447,7 +3447,7 @@ compute_logical_op_length (machine_mode mode, rtx *operands)
   enum rtx_code code = GET_CODE (operands[3]);
   /* Pretend that every byte is affected if both operands are registers.  */
   const unsigned HOST_WIDE_INT intval =
-    (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
+    (unsigned HOST_WIDE_INT) ((CONST_INT_P (operands[2]))
 			      /* Always use the full instruction if the
 				 first operand is in memory.  It is better
 				 to use define_splits to generate the shorter
@@ -3593,7 +3593,7 @@ compute_logical_op_cc (machine_mode mode, rtx *operands)
   enum rtx_code code = GET_CODE (operands[3]);
   /* Pretend that every byte is affected if both operands are registers.  */
   const unsigned HOST_WIDE_INT intval =
-    (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
+    (unsigned HOST_WIDE_INT) ((CONST_INT_P (operands[2]))
 			      /* Always use the full instruction if the
 				 first operand is in memory.  It is better
 				 to use define_splits to generate the shorter
@@ -3755,7 +3755,7 @@ h8sx_classify_shift (machine_mode mode, enum rtx_code code, rtx op)
     case ASHIFT:
     case LSHIFTRT:
       /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd).  */
-      if (GET_CODE (op) != CONST_INT)
+      if (!CONST_INT_P (op))
 	return H8SX_SHIFT_BINARY;
 
       /* Reject out-of-range shift amounts.  */
@@ -3774,7 +3774,7 @@ h8sx_classify_shift (machine_mode mode, enum rtx_code code, rtx op)
       return H8SX_SHIFT_NONE;
 
     case ROTATE:
-      if (GET_CODE (op) == CONST_INT
+      if (CONST_INT_P (op)
 	  && (INTVAL (op) == 1
 	      || INTVAL (op) == 2
 	      || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2
@@ -4610,7 +4610,7 @@ output_a_shift (rtx *operands)
 
   /* This case must be taken care of by one of the two splitters
      that convert a variable shift into a loop.  */
-  gcc_assert (GET_CODE (operands[2]) == CONST_INT);
+  gcc_assert (CONST_INT_P (operands[2]));
   
   n = INTVAL (operands[2]);
 
@@ -4776,7 +4776,7 @@ compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
       gcc_unreachable ();
     }
 
-  if (GET_CODE (operands[2]) != CONST_INT)
+  if (!CONST_INT_P (operands[2]))
     {
       /* Get the assembler code to do one shift.  */
       get_shift_alg (shift_type, shift_mode, 1, &info);
@@ -4926,7 +4926,7 @@ compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
 
   /* This case must be taken care of by one of the two splitters
      that convert a variable shift into a loop.  */
-  gcc_assert (GET_CODE (operands[2]) == CONST_INT);
+  gcc_assert (CONST_INT_P (operands[2]));
   
   n = INTVAL (operands[2]);
 
@@ -4990,7 +4990,7 @@ expand_a_rotate (rtx operands[])
   /* We rotate in place.  */
   emit_move_insn (dst, src);
 
-  if (GET_CODE (rotate_amount) != CONST_INT)
+  if (!CONST_INT_P (rotate_amount))
     {
       rtx counter = gen_reg_rtx (QImode);
       rtx_code_label *start_label = gen_label_rtx ();
@@ -5068,7 +5068,7 @@ output_a_rotate (enum rtx_code code, rtx *operands)
   int amount;
   machine_mode mode = GET_MODE (dst);
 
-  gcc_assert (GET_CODE (rotate_amount) == CONST_INT);
+  gcc_assert (CONST_INT_P (rotate_amount));
 
   switch (mode)
     {
@@ -5173,7 +5173,7 @@ compute_a_rotate_length (rtx *operands)
   int amount;
   unsigned int length = 0;
 
-  gcc_assert (GET_CODE (amount_rtx) == CONST_INT);
+  gcc_assert (CONST_INT_P (amount_rtx));
 
   amount = INTVAL (amount_rtx);
 
@@ -5629,7 +5629,7 @@ h8300_eightbit_constant_address_p (rtx x)
       && (SYMBOL_REF_FLAGS (XEXP (XEXP (x, 0), 0)) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0)
     return 1;
 
-  if (GET_CODE (x) != CONST_INT)
+  if (!CONST_INT_P (x))
     return 0;
 
   addr = INTVAL (x);
@@ -5700,7 +5700,7 @@ byte_accesses_mergeable_p (rtx addr1, rtx addr2)
     }
   else if (GET_CODE (addr1) == PLUS
 	   && REG_P (XEXP (addr1, 0))
-	   && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
+	   && CONST_INT_P (XEXP (addr1, 1)))
     {
       reg1 = XEXP (addr1, 0);
       offset1 = INTVAL (XEXP (addr1, 1));
@@ -5715,7 +5715,7 @@ byte_accesses_mergeable_p (rtx addr1, rtx addr2)
     }
   else if (GET_CODE (addr2) == PLUS
 	   && REG_P (XEXP (addr2, 0))
-	   && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
+	   && CONST_INT_P (XEXP (addr2, 1)))
     {
       reg2 = XEXP (addr2, 0);
       offset2 = INTVAL (XEXP (addr2, 1));
diff --git a/gcc/config/h8300/h8300.h b/gcc/config/h8300/h8300.h
index e50521a7b64..7a676f7ba8d 100644
--- a/gcc/config/h8300/h8300.h
+++ b/gcc/config/h8300/h8300.h
@@ -478,7 +478,7 @@ struct cum_arg
 
 #define CONSTANT_ADDRESS_P(X)					\
   (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF	\
-   || (GET_CODE (X) == CONST_INT				\
+   || (CONST_INT_P (X)				\
        /* We handle signed and unsigned offsets here.  */	\
        && INTVAL (X) > (TARGET_H8300 ? -0x10000 : -0x1000000)	\
        && INTVAL (X) < (TARGET_H8300 ? 0x10000 : 0x1000000))	\
diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md
index 778d3e1d132..5f3b98da929 100644
--- a/gcc/config/h8300/h8300.md
+++ b/gcc/config/h8300/h8300.md
@@ -349,7 +349,7 @@
 	}
       else
 	{
-	  if (GET_CODE (operands[1]) == CONST_INT)
+	  if (CONST_INT_P (operands[1]))
 	    {
 	      /* If either half is zero, use sub.w to clear that
 		 half.  */
@@ -395,7 +395,7 @@
     case 9:
       return "stmac	macl,%0";
     default:
-      if (GET_CODE (operands[1]) == CONST_INT)
+      if (CONST_INT_P (operands[1]))
 	{
 	  int val = INTVAL (operands[1]);
 
@@ -2945,8 +2945,8 @@
   {
     if (TARGET_H8300SX)
       {
-	if (GET_CODE (operands[1]) == CONST_INT
-	    && GET_CODE (operands[2]) == CONST_INT
+	if (CONST_INT_P (operands[1])
+	    && CONST_INT_P (operands[2])
 	    && INTVAL (operands[1]) <= 8
 	    && INTVAL (operands[2]) >= 0
 	    && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8
@@ -2954,7 +2954,7 @@
 	  {
 	    /* If the source operand is zero, it's better to use AND rather
 	       than BFST.  Likewise OR if the operand is all ones.  */
-	    if (GET_CODE (operands[3]) == CONST_INT)
+	    if (CONST_INT_P (operands[3]))
 	      {
 		HOST_WIDE_INT mask = (1 << INTVAL (operands[1])) - 1;
 		if ((INTVAL (operands[3]) & mask) == 0)
@@ -3016,8 +3016,8 @@
   {
     if (TARGET_H8300SX)
       {
-	if (GET_CODE (operands[2]) == CONST_INT
-	    && GET_CODE (operands[3]) == CONST_INT
+	if (CONST_INT_P (operands[2])
+	    && CONST_INT_P (operands[3])
 	    && INTVAL (operands[2]) <= 8
 	    && INTVAL (operands[3]) >= 0
 	    && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8
@@ -3167,7 +3167,7 @@
 	  (match_operand 4 "h8300_src_operand" "I,rQi")]))]
   "TARGET_H8300SX
    && (GET_MODE (operands[3]) == GET_MODE (operands[4])
-       || GET_CODE (operands[4]) == CONST_INT)
+       || CONST_INT_P (operands[4]))
    && GET_MODE_CLASS (GET_MODE (operands[3])) == MODE_INT
    && GET_MODE_SIZE (GET_MODE (operands[3])) <= 4"
   "#"
diff --git a/gcc/config/h8300/predicates.md b/gcc/config/h8300/predicates.md
index 70c6c5c1765..14b0604ed64 100644
--- a/gcc/config/h8300/predicates.md
+++ b/gcc/config/h8300/predicates.md
@@ -70,7 +70,7 @@
 (define_predicate "nibble_operand"
   (match_code "const_int")
 {
-  return (GET_CODE (op) == CONST_INT && TARGET_H8300SX
+  return (CONST_INT_P (op) && TARGET_H8300SX
 	  && INTVAL (op) >= 0 && INTVAL (op) <= 15);
 })
 
@@ -186,7 +186,7 @@
 (define_predicate "single_one_operand"
   (match_code "const_int")
 {
-  if (GET_CODE (op) == CONST_INT)
+  if (CONST_INT_P (op))
     {
       /* We really need to do this masking because 0x80 in QImode is
 	 represented as -128 for example.  */
@@ -203,7 +203,7 @@
 (define_predicate "single_zero_operand"
   (match_code "const_int")
 {
-  if (GET_CODE (op) == CONST_INT)
+  if (CONST_INT_P (op))
     {
       /* We really need to do this masking because 0x80 in QImode is
 	 represented as -128 for example.  */
@@ -288,7 +288,7 @@
   if (TARGET_H8300SX)
     return 0;
 
-  if (GET_CODE (op) == CONST_INT)
+  if (CONST_INT_P (op))
     {
       HOST_WIDE_INT value = INTVAL (op);
 
@@ -370,7 +370,7 @@
 {
   return (GET_CODE (op) == MEM
           && (GET_CODE (XEXP (op, 0)) == REG
-              || GET_CODE (XEXP (op, 0)) == CONST_INT));
+              || CONST_INT_P (XEXP (op, 0))));
 })
 
 ;; Return nonzero if X is a stack pointer.
@@ -401,7 +401,7 @@
 (define_predicate "const_int_gt_2_operand"
   (match_code "const_int")
 {
-  return (GET_CODE (op) == CONST_INT
+  return (CONST_INT_P (op)
 	  && abs (INTVAL (op)) > 2);
 })
 
@@ -411,7 +411,7 @@
 (define_predicate "const_int_ge_8_operand"
   (match_code "const_int")
 {
-  return (GET_CODE (op) == CONST_INT
+  return (CONST_INT_P (op)
 	  && abs (INTVAL (op)) >= 8);
 })
 
@@ -420,7 +420,7 @@
 (define_predicate "const_int_qi_operand"
   (match_code "const_int")
 {
-  return (GET_CODE (op) == CONST_INT
+  return (CONST_INT_P (op)
 	  && (INTVAL (op) & 0xff) == INTVAL (op));
 })
 
@@ -429,7 +429,7 @@
 (define_predicate "const_int_hi_operand"
   (match_code "const_int")
 {
-  return (GET_CODE (op) == CONST_INT
+  return (CONST_INT_P (op)
 	  && (INTVAL (op) & 0xffff) == INTVAL (op));
 })
 
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index a2a6c5cffa1..e9ee4c707bd 100644
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -930,7 +930,7 @@ ia64_load_pair_ok (rtx dst, rtx src)
       {
 	rtx adjust = XEXP (XEXP (XEXP (src, 0), 1), 1);
 
-	if (GET_CODE (adjust) != CONST_INT
+	if (!CONST_INT_P (adjust)
 	    || INTVAL (adjust) != GET_MODE_SIZE (GET_MODE (src)))
 	  return 0;
       }
@@ -1074,7 +1074,7 @@ ia64_legitimate_constant_p (machine_mode mode, rtx x)
 
 	  if (GET_CODE (op) == CONST
 	      && GET_CODE (XEXP (op, 0)) == PLUS
-	      && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
+	      && CONST_INT_P (XEXP (XEXP (op, 0), 1)))
 	    {
 	      addend = INTVAL (XEXP (XEXP (op, 0), 1));
 	      op = XEXP (XEXP (op, 0), 0);
@@ -1333,7 +1333,7 @@ ia64_expand_move (rtx op0, rtx op1)
 
       if (GET_CODE (op1) == CONST
 	  && GET_CODE (XEXP (op1, 0)) == PLUS
-	  && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT)
+	  && CONST_INT_P (XEXP (XEXP (op1, 0), 1)))
 	{
 	  addend = INTVAL (XEXP (XEXP (op1, 0), 1));
 	  sym = XEXP (XEXP (op1, 0), 0);
@@ -1531,7 +1531,7 @@ ia64_split_tmode (rtx out[2], rtx in, bool reversed, bool dead)
 	      }
 	    else
 	      {
-		gcc_assert (GET_CODE (XEXP (offset, 1)) == CONST_INT);
+		gcc_assert (CONST_INT_P (XEXP (offset, 1)));
 		if (INTVAL (XEXP (offset, 1)) < -256 + 8)
 		  {
 		    /* Again the postmodify cannot be made to match,
@@ -5495,7 +5495,7 @@ ia64_print_operand (FILE * file, rtx x, int code)
 
 	  case POST_MODIFY:
 	    x = XEXP (XEXP (XEXP (x, 0), 1), 1);
-	    if (GET_CODE (x) == CONST_INT)
+	    if (CONST_INT_P (x))
 	      value = INTVAL (x);
 	    else
 	      {
@@ -5539,7 +5539,7 @@ ia64_print_operand (FILE * file, rtx x, int code)
       return;
 
     case 'T':
-      if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
+      if (! TARGET_GNU_AS && CONST_INT_P (x))
 	{
 	  fprintf (file, "0x%x", (int) INTVAL (x) & 0xffffffff);
 	  return;
@@ -5547,7 +5547,7 @@ ia64_print_operand (FILE * file, rtx x, int code)
       break;
 
     case 'U':
-      if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
+      if (! TARGET_GNU_AS && CONST_INT_P (x))
 	{
 	  const char *prefix = "0x";
 	  if (INTVAL (x) & 0x80000000)
@@ -5574,7 +5574,7 @@ ia64_print_operand (FILE * file, rtx x, int code)
 	fputs (reg_names[REGNO (x)], file);
       else if (x == CONST0_RTX (GET_MODE (x)))
 	fputs ("r0", file);
-      else if (GET_CODE (x) == CONST_INT)
+      else if (CONST_INT_P (x))
 	output_addr_const (file, x);
       else
 	output_operand_lossage ("invalid %%r value");
@@ -5948,7 +5948,7 @@ ia64_secondary_reload_class (enum reg_class rclass,
       /* This can happen because of the ior/and/etc patterns that accept FP
 	 registers as operands.  If the third operand is a constant, then it
 	 needs to be reloaded into a FP register.  */
-      if (GET_CODE (x) == CONST_INT)
+      if (CONST_INT_P (x))
 	return GR_REGS;
 
       /* This can happen because of register elimination in a muldi3 insn.
@@ -10076,7 +10076,7 @@ process_cfa_adjust_cfa (FILE *asm_out_file, rtx pat, rtx insn,
 	  rtx op0 = XEXP (src, 0);
 	  rtx op1 = XEXP (src, 1);
 	  
-	  gcc_assert (op0 == dest && GET_CODE (op1) == CONST_INT);
+	  gcc_assert (op0 == dest && CONST_INT_P (op1));
 	  
 	  if (INTVAL (op1) < 0)
 	    {
@@ -10179,7 +10179,7 @@ process_cfa_offset (FILE *asm_out_file, rtx pat, bool unwind)
   else
     {
       gcc_assert (GET_CODE (XEXP (dest, 0)) == PLUS
-		  && GET_CODE (XEXP (XEXP (dest, 0), 1)) == CONST_INT);
+		  && CONST_INT_P (XEXP (XEXP (dest, 0), 1)));
       base = XEXP (XEXP (dest, 0), 0);
       off = INTVAL (XEXP (XEXP (dest, 0), 1));
     }
diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md
index 037006cdbfa..5d55b190334 100644
--- a/gcc/config/ia64/ia64.md
+++ b/gcc/config/ia64/ia64.md
@@ -3237,7 +3237,7 @@
 		   (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
   ""
 {
-  if (GET_CODE (operands[2]) != CONST_INT)
+  if (!CONST_INT_P (operands[2]))
     {
       /* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED?  Now
 	 we've got to get rid of stray bits outside the SImode register.  */
@@ -3265,7 +3265,7 @@
   ""
 {
   rtx subtarget = gen_reg_rtx (DImode);
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]),
 			 GEN_INT (32 - INTVAL (operands[2])), operands[2]));
   else
@@ -3286,7 +3286,7 @@
   ""
 {
   rtx subtarget = gen_reg_rtx (DImode);
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]),
 			  GEN_INT (32 - INTVAL (operands[2])), operands[2]));
   else
diff --git a/gcc/config/ia64/predicates.md b/gcc/config/ia64/predicates.md
index 4293bcbad2c..f3a34865055 100644
--- a/gcc/config/ia64/predicates.md
+++ b/gcc/config/ia64/predicates.md
@@ -45,7 +45,7 @@
       op = XEXP (op, 0);
       if (GET_CODE (op) != PLUS
 	  || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
-	  || GET_CODE (XEXP (op, 1)) != CONST_INT)
+	  || !CONST_INT_P (XEXP (op, 1)))
 	return false;
       offset = INTVAL (XEXP (op, 1));
       op = XEXP (op, 0);
@@ -110,7 +110,7 @@
       op = XEXP (op, 0);
       if (GET_CODE (op) != PLUS
 	  || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
-	  || GET_CODE (XEXP (op, 1)) != CONST_INT)
+	  || !CONST_INT_P (XEXP (op, 1)))
 	return false;
       op = XEXP (op, 0);
       /* FALLTHRU */
@@ -133,7 +133,7 @@
       op = XEXP (op, 0);
       if (GET_CODE (op) != PLUS
 	  || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
-	  || GET_CODE (XEXP (op, 1)) != CONST_INT)
+	  || !CONST_INT_P (XEXP (op, 1)))
 	return false;
       op = XEXP (op, 0);
       /* FALLTHRU */
@@ -184,7 +184,7 @@
       op = XEXP (op, 0);
       if (GET_CODE (op) != PLUS
 	  || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
-          || GET_CODE (XEXP (op, 1)) != CONST_INT)
+          || !CONST_INT_P (XEXP (op, 1)))
         return false;
 
       addend = INTVAL (XEXP (op, 1));
@@ -227,7 +227,7 @@
       op = XEXP (op, 0);
       if (GET_CODE (op) != PLUS
 	  || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
-	  || GET_CODE (XEXP (op, 1)) != CONST_INT)
+	  || !CONST_INT_P (XEXP (op, 1)))
 	return false;
 
       /* We only allow certain offsets for certain tls models.  */
@@ -267,7 +267,7 @@
       op = XEXP (op, 0);
       if (GET_CODE (op) != PLUS
 	  || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
-	  || GET_CODE (XEXP (op, 1)) != CONST_INT
+	  || !CONST_INT_P (XEXP (op, 1))
 	  || (INTVAL (XEXP (op, 1)) & 0x3fff) != 0)
 	return false;
       op = XEXP (op, 0);
@@ -291,7 +291,7 @@
       op = XEXP (op, 0);
       if (GET_CODE (op) != PLUS
           || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
-          || GET_CODE (XEXP (op, 1)) != CONST_INT)
+          || !CONST_INT_P (XEXP (op, 1)))
         return false;
       op = XEXP (op, 0);
       /* FALLTHRU */
@@ -337,7 +337,7 @@
 	op = XEXP (op, 0);
 	if (GET_CODE (op) != PLUS
 	    || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
-            || GET_CODE (XEXP (op, 1)) != CONST_INT)
+            || !CONST_INT_P (XEXP (op, 1)))
 	  return false;
 
 	addend = INTVAL (XEXP (op, 1));
diff --git a/gcc/config/ia64/vect.md b/gcc/config/ia64/vect.md
index 2f17947a0e4..2f8615ed131 100644
--- a/gcc/config/ia64/vect.md
+++ b/gcc/config/ia64/vect.md
@@ -1024,7 +1024,7 @@
   rtx op2 = XVECEXP (operands[1], 0, 1);
   rtx x;
 
-  if (GET_CODE (op1) == CONST_INT && GET_CODE (op2) == CONST_INT)
+  if (CONST_INT_P (op1) && CONST_INT_P (op2))
     {
       x = gen_rtx_CONST_VECTOR (V2SImode, XVEC (operands[1], 0));
       emit_move_insn (operands[0], x);
diff --git a/gcc/config/iq2000/iq2000.c b/gcc/config/iq2000/iq2000.c
index c3be6fa0eca..fd290d096ae 100644
--- a/gcc/config/iq2000/iq2000.c
+++ b/gcc/config/iq2000/iq2000.c
@@ -328,7 +328,7 @@ iq2000_legitimate_address_p (machine_mode mode, rtx xinsn, bool strict)
      accept (subreg (const_int)) which will fail to reload.  */
   if (CONSTANT_ADDRESS_P (xinsn)
       && ! (iq2000_check_split (xinsn, mode))
-      && ! (GET_CODE (xinsn) == CONST_INT && ! SMALL_INT (xinsn)))
+      && ! (CONST_INT_P (xinsn) && ! SMALL_INT (xinsn)))
     return 1;
 
   while (GET_CODE (xinsn) == SUBREG)
@@ -729,7 +729,7 @@ iq2000_move_1word (rtx operands[], rtx_insn *insn, int unsignedp)
 	  rtx add_op1 = XEXP (op1, 1);
 
 	  if (GET_CODE (XEXP (op1, 1)) == REG
-	      && GET_CODE (XEXP (op1, 0)) == CONST_INT)
+	      && CONST_INT_P (XEXP (op1, 0)))
 	    add_op0 = XEXP (op1, 1), add_op1 = XEXP (op1, 0);
 
 	  operands[2] = add_op0;
@@ -959,7 +959,7 @@ gen_int_relational (enum rtx_code test_code, rtx result, rtx cmp0, rtx cmp1,
       if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
 	{
 	  /* Comparisons against zero are simple branches.  */
-	  if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
+	  if (CONST_INT_P (cmp1) && INTVAL (cmp1) == 0)
 	    return 0;
 
 	  /* Test for beq/bne.  */
@@ -972,10 +972,10 @@ gen_int_relational (enum rtx_code test_code, rtx result, rtx cmp0, rtx cmp1,
     }
 
   /* Make sure we can handle any constants given to us.  */
-  if (GET_CODE (cmp0) == CONST_INT)
+  if (CONST_INT_P (cmp0))
     cmp0 = force_reg (mode, cmp0);
 
-  if (GET_CODE (cmp1) == CONST_INT)
+  if (CONST_INT_P (cmp1))
     {
       HOST_WIDE_INT value = INTVAL (cmp1);
 
@@ -985,7 +985,7 @@ gen_int_relational (enum rtx_code test_code, rtx result, rtx cmp0, rtx cmp1,
     }
 
   /* See if we need to invert the result.  */
-  invert = (GET_CODE (cmp1) == CONST_INT
+  invert = (CONST_INT_P (cmp1)
 	    ? p_info->invert_const : p_info->invert_reg);
 
   if (p_invert != (int *)0)
@@ -996,7 +996,7 @@ gen_int_relational (enum rtx_code test_code, rtx result, rtx cmp0, rtx cmp1,
 
   /* Comparison to constants, may involve adding 1 to change a LT into LE.
      Comparison between two registers, may involve switching operands.  */
-  if (GET_CODE (cmp1) == CONST_INT)
+  if (CONST_INT_P (cmp1))
     {
       if (p_info->const_add != 0)
 	{
@@ -1029,7 +1029,7 @@ gen_int_relational (enum rtx_code test_code, rtx result, rtx cmp0, rtx cmp1,
       cmp1 = temp;
     }
 
-  if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
+  if (test == ITEST_NE && CONST_INT_P (cmp1) && INTVAL (cmp1) == 0)
     reg = cmp0;
   else
     {
@@ -1086,7 +1086,7 @@ gen_conditional_branch (rtx operands[], machine_mode mode)
       cmp1 = const0_rtx;
       test_code = NE;
     }
-  else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
+  else if (CONST_INT_P (cmp1) && INTVAL (cmp1) != 0)
     /* We don't want to build a comparison against a nonzero
        constant.  */
     cmp1 = force_reg (mode, cmp1);
@@ -2639,7 +2639,7 @@ expand_one_builtin (enum insn_code icode, rtx target, tree exp,
       arg[i] = CALL_EXPR_ARG (exp, i);
       op[i] = expand_normal (arg[i]);
       mode[i] = insn_data[icode].operand[i].mode;
-      if (code[i] == CONST_INT && GET_CODE (op[i]) != CONST_INT)
+      if (code[i] == CONST_INT && !CONST_INT_P (op[i]))
 	error ("argument %qd is not a constant", i + 1);
       if (code[i] == REG
 	  && ! (*insn_data[icode].operand[i].predicate) (op[i], mode[i]))
@@ -3012,7 +3012,7 @@ iq2000_print_operand_address (FILE * file, machine_mode mode, rtx addr)
       case CONST_INT:
       case CONST:
 	output_addr_const (file, addr);
-	if (GET_CODE (addr) == CONST_INT)
+	if (CONST_INT_P (addr))
 	  fprintf (file, "(%s)", reg_names [0]);
 	break;
 
@@ -3231,16 +3231,16 @@ iq2000_print_operand (FILE *file, rtx op, int letter)
       fputs (s, file);
     }
 
-  else if (letter == 'x' && GET_CODE (op) == CONST_INT)
+  else if (letter == 'x' && CONST_INT_P (op))
     fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
 
-  else if (letter == 'X' && GET_CODE(op) == CONST_INT)
+  else if (letter == 'X' && CONST_INT_P (op))
     fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & (INTVAL (op) >> 16));
 
-  else if (letter == 'd' && GET_CODE(op) == CONST_INT)
+  else if (letter == 'd' && CONST_INT_P (op))
     fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
 
-  else if (letter == 'z' && GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
+  else if (letter == 'z' && CONST_INT_P (op) && INTVAL (op) == 0)
     fputs (reg_names[GP_REG_FIRST], file);
 
   else if (letter == 'd' || letter == 'x' || letter == 'X')
@@ -3370,7 +3370,7 @@ iq2000_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
     case ASHIFTRT:
     case LSHIFTRT:
       if (mode == DImode)
-	* total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT) ? 4 : 12);
+	* total = COSTS_N_INSNS ((CONST_INT_P (XEXP (x, 1))) ? 4 : 12);
       else
 	* total = COSTS_N_INSNS (1);
     break;								
diff --git a/gcc/config/iq2000/iq2000.h b/gcc/config/iq2000/iq2000.h
index 89efdafe4e0..04a36ab35b1 100644
--- a/gcc/config/iq2000/iq2000.h
+++ b/gcc/config/iq2000/iq2000.h
@@ -346,7 +346,7 @@ typedef struct iq2000_args
 
 #define CONSTANT_ADDRESS_P(X)						\
   (   (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
-    || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH		\
+    || CONST_INT_P (X) || GET_CODE (X) == HIGH		\
     || (GET_CODE (X) == CONST)))
 
 #define MAX_REGS_PER_ADDRESS 1
diff --git a/gcc/config/iq2000/iq2000.md b/gcc/config/iq2000/iq2000.md
index 3363a144dd3..580f22c0d28 100644
--- a/gcc/config/iq2000/iq2000.md
+++ b/gcc/config/iq2000/iq2000.md
@@ -703,7 +703,7 @@
   if ((reload_in_progress | reload_completed) == 0
       && !register_operand (operands[0], SImode)
       && !register_operand (operands[1], SImode)
-      && (GET_CODE (operands[1]) != CONST_INT
+      && (!CONST_INT_P (operands[1])
 	  || INTVAL (operands[1]) != 0))
     {
       rtx temp = force_reg (SImode, operands[1]);
@@ -734,7 +734,7 @@
 	(match_operand:SI 1 "move_operand" "d,IKL,Mnis,R,m,dJ,dJ"))]
   "(register_operand (operands[0], SImode)
        || register_operand (operands[1], SImode)
-       || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
+       || (CONST_INT_P (operands[1]) && INTVAL (operands[1]) == 0))"
   "* return iq2000_move_1word (operands, insn, FALSE);"
   [(set_attr "type"	"move,arith,arith,load,load,store,store")
    (set_attr "mode"	"SI")
@@ -756,7 +756,7 @@
   if ((reload_in_progress | reload_completed) == 0
       && !register_operand (operands[0], HImode)
       && !register_operand (operands[1], HImode)
-      && ((GET_CODE (operands[1]) != CONST_INT
+      && ((!CONST_INT_P (operands[1])
 	  || INTVAL (operands[1]) != 0)))
     {
       rtx temp = force_reg (HImode, operands[1]);
@@ -773,7 +773,7 @@
 	(match_operand:HI 1 "general_operand"       "d,IK,R,m,dJ,dJ"))]
   "(register_operand (operands[0], HImode)
        || register_operand (operands[1], HImode)
-       || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
+       || (CONST_INT_P (operands[1]) && INTVAL (operands[1]) == 0))"
   "* return iq2000_move_1word (operands, insn, TRUE);"
   [(set_attr "type"	"move,arith,load,load,store,store")
    (set_attr "mode"	"HI")
@@ -795,7 +795,7 @@
   if ((reload_in_progress | reload_completed) == 0
       && !register_operand (operands[0], QImode)
       && !register_operand (operands[1], QImode)
-      && (GET_CODE (operands[1]) != CONST_INT
+      && (!CONST_INT_P (operands[1])
           || INTVAL (operands[1]) != 0))
     {
       rtx temp = force_reg (QImode, operands[1]);
@@ -812,7 +812,7 @@
 	(match_operand:QI 1 "general_operand"       "d,IK,R,m,dJ,dJ"))]
   "(register_operand (operands[0], QImode)
        || register_operand (operands[1], QImode)
-       || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
+       || (CONST_INT_P (operands[1]) && INTVAL (operands[1]) == 0))"
   "* return iq2000_move_1word (operands, insn, TRUE);"
   [(set_attr "type"	"move,arith,load,load,store,store")
    (set_attr "mode"	"QI")
@@ -914,7 +914,7 @@
   ""
   "*
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     {
       operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
       return \"sll\\t%0,%1,%2\";
@@ -939,7 +939,7 @@
   ""
   "*
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     {
       operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
       return \"sra\\t%0,%1,%2\";
@@ -964,7 +964,7 @@
   ""
   "*
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     {
       operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
       return \"srl\\t%0,%1,%2\";
@@ -1555,7 +1555,7 @@
 {
   register rtx target = operands[0];
 
-  if (GET_CODE (target) == CONST_INT)
+  if (CONST_INT_P (target))
     return \"li\\t%@,%0\\n\\tjalr\\t%2,%@\";
   else if (CONSTANT_ADDRESS_P (target))
     return \"jal\\t%0\";
@@ -1643,7 +1643,7 @@
 {
   register rtx target = operands[1];
 
-  if (GET_CODE (target) == CONST_INT)
+  if (CONST_INT_P (target))
     return \"li\\t%@,%1\\n\\tjalr\\t%3,%@\";
   else if (CONSTANT_ADDRESS_P (target))
     return \"jal\\t%1\";
@@ -1680,7 +1680,7 @@
 {
   register rtx target = operands[1];
 
-  if (GET_CODE (target) == CONST_INT)
+  if (CONST_INT_P (target))
     return \"li\\t%@,%1\\n\\tjalr\\t%4,%@\";
   else if (CONSTANT_ADDRESS_P (target))
     return \"jal\\t%1\";
diff --git a/gcc/config/iq2000/predicates.md b/gcc/config/iq2000/predicates.md
index 8d648cdb3d5..93fa4737648 100644
--- a/gcc/config/iq2000/predicates.md
+++ b/gcc/config/iq2000/predicates.md
@@ -23,7 +23,7 @@
 (define_predicate "uns_arith_operand"
   (match_code "reg,const_int,subreg")
 {
-  if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
+  if (CONST_INT_P (op) && SMALL_INT_UNSIGNED (op))
     return 1;
 
   return register_operand (op, mode);
@@ -35,7 +35,7 @@
 (define_predicate "arith_operand"
   (match_code "reg,const_int,subreg")
 {
-  if (GET_CODE (op) == CONST_INT && SMALL_INT (op))
+  if (CONST_INT_P (op) && SMALL_INT (op))
     return 1;
 
   return register_operand (op, mode);
@@ -54,7 +54,7 @@
 (define_predicate "small_int"
   (match_code "const_int")
 {
-  return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
+  return (CONST_INT_P (op) && SMALL_INT (op));
 })
 
 ;; Return 1 if OP is a 32-bit integer which is too big to be loaded
@@ -65,7 +65,7 @@
 {
   HOST_WIDE_INT value;
 
-  if (GET_CODE (op) != CONST_INT)
+  if (!CONST_INT_P (op))
     return 0;
 
   value = INTVAL (op);
@@ -140,12 +140,12 @@
       plus0 = XEXP (addr, 0);
       plus1 = XEXP (addr, 1);
       if (GET_CODE (plus0) == REG
-	  && GET_CODE (plus1) == CONST_INT && SMALL_INT (plus1)
+	  && CONST_INT_P (plus1) && SMALL_INT (plus1)
 	  && SMALL_INT_UNSIGNED (plus1) /* No negative offsets.  */)
 	return 1;
 
       else if (GET_CODE (plus1) == REG
-	       && GET_CODE (plus0) == CONST_INT && SMALL_INT (plus0)
+	       && CONST_INT_P (plus0) && SMALL_INT (plus0)
 	       && SMALL_INT_UNSIGNED (plus1) /* No negative offsets.  */)
 	return 1;
 
@@ -231,7 +231,7 @@
 {
   int intval;
 
-  if (GET_CODE (op) != CONST_INT)
+  if (!CONST_INT_P (op))
     return 0;
   else
     intval = INTVAL (op);
diff --git a/gcc/config/lm32/lm32.c b/gcc/config/lm32/lm32.c
index 7ed9ac00f08..2b04d48f97e 100644
--- a/gcc/config/lm32/lm32.c
+++ b/gcc/config/lm32/lm32.c
@@ -227,12 +227,12 @@ gen_int_relational (enum rtx_code code,
   else
     {
       /* We can't have const_ints in cmp0, other than 0.  */
-      if ((GET_CODE (cmp0) == CONST_INT) && (INTVAL (cmp0) != 0))
+      if ((CONST_INT_P (cmp0)) && (INTVAL (cmp0) != 0))
 	cmp0 = force_reg (mode, cmp0);
 
       /* If the comparison is against an int not in legal range
          move it into a register.  */
-      if (GET_CODE (cmp1) == CONST_INT)
+      if (CONST_INT_P (cmp1))
 	{
 	  switch (code)
 	    {
@@ -519,7 +519,7 @@ lm32_print_operand (FILE * file, rtx op, int letter)
     output_addr_const (file, XEXP (op, 0));  
   else if (code == MEM)
     output_address (GET_MODE (op), XEXP (op, 0));
-  else if (letter == 'z' && GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
+  else if (letter == 'z' && CONST_INT_P (op) && INTVAL (op) == 0)
     fprintf (file, "%s", reg_names[0]);
   else if (GET_CODE (op) == CONST_DOUBLE)
     {
@@ -581,7 +581,7 @@ lm32_print_operand_address (FILE * file, rtx addr)
 
 	if (GET_CODE (arg0) == REG && CONSTANT_P (arg1))
 	  {
-	    if (GET_CODE (arg1) == CONST_INT)
+	    if (CONST_INT_P (arg1))
 	      fprintf (file, "(%s+%ld)", reg_names[REGNO (arg0)],
 		       INTVAL (arg1));
 	    else
@@ -882,7 +882,7 @@ lm32_block_move_inline (rtx dest, rtx src, HOST_WIDE_INT length,
 int
 lm32_expand_block_move (rtx * operands)
 {
-  if ((GET_CODE (operands[2]) == CONST_INT) && (INTVAL (operands[2]) <= 32))
+  if ((CONST_INT_P (operands[2])) && (INTVAL (operands[2]) <= 32))
     {
       lm32_block_move_inline (operands[0], operands[1], INTVAL (operands[2]),
 			      INTVAL (operands[3]));
@@ -997,7 +997,7 @@ lm32_rtx_costs (rtx x, machine_mode mode, int outer_code,
 	  /* FIXME: Guessing here.  */
 	  *total = COSTS_N_INSNS (LM32_NUM_REGS (mode) * 4);
 	}
-      else if (small_mode && GET_CODE (XEXP (x, 1)) == CONST_INT)
+      else if (small_mode && CONST_INT_P (XEXP (x, 1)))
 	{
 	  *total = COSTS_N_INSNS (INTVAL (XEXP (x, 1)));
 	}
@@ -1039,7 +1039,7 @@ lm32_rtx_costs (rtx x, machine_mode mode, int outer_code,
 	    *total = COSTS_N_INSNS (1);
 	  else
 	    {
-	      if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+	      if (CONST_INT_P (XEXP (x, 1)))
 		{
 		  int cycles = 0;
 		  unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
@@ -1217,7 +1217,7 @@ lm32_legitimate_address_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x, bool stric
      && REG_P (XEXP (x, 0))                                     
      && ((strict && STRICT_REG_OK_FOR_BASE_P (XEXP (x, 0)))
          || (!strict && NONSTRICT_REG_OK_FOR_BASE_P (XEXP (x, 0))))                           
-     && GET_CODE (XEXP (x, 1)) == CONST_INT                      
+     && CONST_INT_P (XEXP (x, 1))                      
      && satisfies_constraint_K (XEXP ((x), 1)))
     return true;
               
diff --git a/gcc/config/lm32/lm32.h b/gcc/config/lm32/lm32.h
index c330b176a6b..8e98e37d16a 100644
--- a/gcc/config/lm32/lm32.h
+++ b/gcc/config/lm32/lm32.h
@@ -306,7 +306,7 @@ enum reg_class
 
 #define CONSTANT_ADDRESS_P(X)						\
   ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
-    || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH		\
+    || CONST_INT_P (X) || GET_CODE (X) == HIGH		\
     || (GET_CODE (X) == CONST)))
 
 #define MAX_REGS_PER_ADDRESS 1
diff --git a/gcc/config/lm32/lm32.md b/gcc/config/lm32/lm32.md
index 91a5fe1e004..9c8a72e2a17 100644
--- a/gcc/config/lm32/lm32.md
+++ b/gcc/config/lm32/lm32.md
@@ -200,7 +200,7 @@
 							   operands[1])));
       DONE;
     }  
-  else if (GET_CODE (operands[1]) == CONST_INT)
+  else if (CONST_INT_P (operands[1]))
     {
       if (!(satisfies_constraint_K (operands[1]) 
           || satisfies_constraint_L (operands[1])
diff --git a/gcc/config/m32c/m32c.c b/gcc/config/m32c/m32c.c
index d0d24bb5f2b..08e0542bd2b 100644
--- a/gcc/config/m32c/m32c.c
+++ b/gcc/config/m32c/m32c.c
@@ -1846,7 +1846,7 @@ m32c_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
   if (GET_CODE (x) == PLUS
       && GET_CODE (XEXP (x, 0)) == REG
       && REGNO (XEXP (x, 0)) == FB_REGNO
-      && GET_CODE (XEXP (x, 1)) == CONST_INT
+      && CONST_INT_P (XEXP (x, 1))
       && (INTVAL (XEXP (x, 1)) < -128
 	  || INTVAL (XEXP (x, 1)) > (128 - GET_MODE_SIZE (mode))))
     {
@@ -1885,7 +1885,7 @@ m32c_legitimize_reload_address (rtx * x,
   if (GET_CODE (*x) == PLUS
       && GET_CODE (XEXP (*x, 0)) == REG
       && REGNO (XEXP (*x, 0)) == FB_REGNO
-      && GET_CODE (XEXP (*x, 1)) == CONST_INT
+      && CONST_INT_P (XEXP (*x, 1))
       && (INTVAL (XEXP (*x, 1)) < -128
 	  || INTVAL (XEXP (*x, 1)) > (128 - GET_MODE_SIZE (mode))))
     {
@@ -1908,8 +1908,8 @@ m32c_legitimize_reload_address (rtx * x,
       && GET_CODE (XEXP (*x, 0)) == PLUS
       && GET_CODE (XEXP (XEXP (*x, 0), 0)) == REG
       && REGNO (XEXP (XEXP (*x, 0), 0)) == FB_REGNO
-      && GET_CODE (XEXP (XEXP (*x, 0), 1)) == CONST_INT
-      && GET_CODE (XEXP (*x, 1)) == CONST_INT
+      && CONST_INT_P (XEXP (XEXP (*x, 0), 1))
+      && CONST_INT_P (XEXP (*x, 1))
       )
     {
       if (type == RELOAD_OTHER)
@@ -2230,7 +2230,7 @@ m32c_rtx_costs (rtx x, machine_mode mode, int outer_code,
     case ASHIFT:
     case LSHIFTRT:
     case ASHIFTRT:
-      if (GET_CODE (XEXP (x, 1)) != CONST_INT)
+      if (!CONST_INT_P (XEXP (x, 1)))
 	{
 	  /* mov.b r1l, r1h */
 	  *total +=  COSTS_N_INSNS (1);
@@ -2318,7 +2318,7 @@ m32c_address_cost (rtx addr, machine_mode mode ATTRIBUTE_UNUSED,
     case REG:
       return COSTS_N_INSNS(1);
     case PLUS:
-      if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
+      if (CONST_INT_P (XEXP (addr, 1)))
 	{
 	  i = INTVAL (XEXP (addr, 1));
 	  if (i == 0)
@@ -2598,7 +2598,7 @@ m32c_print_operand (FILE * file, rtx x, int code)
       code = 0;
     }
   /* 'x' and 'X' need to be ignored for non-immediates.  */
-  if ((code == 'x' || code == 'X') && GET_CODE (x) != CONST_INT)
+  if ((code == 'x' || code == 'X') && !CONST_INT_P (x))
     code = 0;
 
   encode_pattern (x);
@@ -3553,8 +3553,8 @@ m32c_expand_setmemhi(rtx *operands)
      most common case.  For counts 8..14 this actually results in
      smaller code with no speed penalty because the half-sized
      constant can be loaded with a shorter opcode.  */
-  if (GET_CODE (count) == CONST_INT
-      && GET_CODE (val) == CONST_INT
+  if (CONST_INT_P (count)
+      && CONST_INT_P (val)
       && ! (INTVAL (count) & 1)
       && (INTVAL (count) > 1)
       && (INTVAL (val) <= 7 && INTVAL (val) >= -8))
@@ -3614,7 +3614,7 @@ m32c_expand_cpymemhi(rtx *operands)
     srca = copy_to_mode_reg (Pmode, srca);
 
   /* Similar to setmem, but we don't need to check the value.  */
-  if (GET_CODE (count) == CONST_INT
+  if (CONST_INT_P (count)
       && ! (INTVAL (count) & 1)
       && (INTVAL (count) > 1))
     {
@@ -3732,7 +3732,7 @@ m32c_prepare_shift (rtx * operands, int scale, int shift_code)
   shift_gen_func func = shift_gen_func_for (mode, shift_code);
   rtx temp;
 
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     {
       int maxc = TARGET_A24 && (mode == PSImode || mode == SImode) ? 32 : 8;
       int count = INTVAL (operands[2]) * scale;
@@ -3844,7 +3844,7 @@ m32c_expand_neg_mulpsi3 (rtx * operands)
 
   temp1 = gen_reg_rtx (SImode);
   temp2 = gen_reg_rtx (SImode);
-  if (GET_CODE (operands[2]) != CONST_INT)
+  if (!CONST_INT_P (operands[2]))
     {
       scale = gen_reg_rtx (SImode);
       emit_insn (gen_zero_extendpsisi2 (scale, operands[2]));
@@ -3866,8 +3866,8 @@ m32c_expand_movcc (rtx *operands)
 
   if (GET_CODE (rel) != EQ && GET_CODE (rel) != NE)
     return 1;
-  if (GET_CODE (operands[2]) != CONST_INT
-      || GET_CODE (operands[3]) != CONST_INT)
+  if (!CONST_INT_P (operands[2])
+      || !CONST_INT_P (operands[3]))
     return 1;
   if (GET_CODE (rel) == NE)
     {
@@ -3896,7 +3896,7 @@ m32c_expand_insv (rtx *operands)
     return 1;
 
   /* Our insv opcode (bset, bclr) can only insert a one-bit constant.  */
-  if (GET_CODE (operands[3]) != CONST_INT)
+  if (!CONST_INT_P (operands[3]))
     return 1;
   if (INTVAL (operands[3]) != 0
       && INTVAL (operands[3]) != 1
diff --git a/gcc/config/m32c/muldiv.md b/gcc/config/m32c/muldiv.md
index 502baff9b65..4ce774c72e7 100644
--- a/gcc/config/m32c/muldiv.md
+++ b/gcc/config/m32c/muldiv.md
@@ -149,7 +149,7 @@
 	(mult:PSI (match_operand:PSI 1 "mra_operand" "%0")
 		  (match_operand 2 "m32c_psi_scale" "Ilb")))]
   "TARGET_A24"
-  "if (GET_CODE (operands[2]) != CONST_INT
+  "if (!CONST_INT_P (operands[2])
        || ! m32c_psi_scale (operands[2], PSImode))
      {
        m32c_expand_neg_mulpsi3 (operands);
diff --git a/gcc/config/m32c/predicates.md b/gcc/config/m32c/predicates.md
index d3d307907ec..93cd9173f75 100644
--- a/gcc/config/m32c/predicates.md
+++ b/gcc/config/m32c/predicates.md
@@ -199,9 +199,9 @@
     rtx pos = XEXP (op, 2);
     return (GET_CODE (reg) == REG
 	    && REGNO (reg) == R1_REGNO
-	    && GET_CODE (size) == CONST_INT
+	    && CONST_INT_P (size)
 	    && INTVAL (size) == 8
-	    && GET_CODE (pos) == CONST_INT
+	    && CONST_INT_P (pos)
 	    && INTVAL (pos) == 8);
   })
 
diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c
index ca89f37935e..fa0e5d2f718 100644
--- a/gcc/config/m68k/m68k.c
+++ b/gcc/config/m68k/m68k.c
@@ -1802,7 +1802,7 @@ output_btst (rtx *operands, rtx countop, rtx dataop, rtx_insn *insn, int signpos
   operands[0] = countop;
   operands[1] = dataop;
 
-  if (GET_CODE (countop) == CONST_INT)
+  if (CONST_INT_P (countop))
     {
       register int count = INTVAL (countop);
       /* If COUNT is bigger than size of storage unit in use,
@@ -1900,7 +1900,7 @@ m68k_decompose_index (rtx x, bool strict_p, struct m68k_address *address)
   scale = 1;
   if ((TARGET_68020 || TARGET_COLDFIRE)
       && GET_CODE (x) == MULT
-      && GET_CODE (XEXP (x, 1)) == CONST_INT
+      && CONST_INT_P (XEXP (x, 1))
       && (INTVAL (XEXP (x, 1)) == 2
 	  || INTVAL (XEXP (x, 1)) == 4
 	  || (INTVAL (XEXP (x, 1)) == 8
@@ -2031,7 +2031,7 @@ m68k_decompose_address (machine_mode mode, rtx x,
 
   /* Check for (d16,An) (mode 5).  */
   if (GET_CODE (x) == PLUS
-      && GET_CODE (XEXP (x, 1)) == CONST_INT
+      && CONST_INT_P (XEXP (x, 1))
       && IN_RANGE (INTVAL (XEXP (x, 1)), -0x8000, 0x8000 - reach)
       && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p))
     {
@@ -2117,7 +2117,7 @@ m68k_decompose_address (machine_mode mode, rtx x,
     {
       /* Check for a nonzero base displacement.  */
       if (GET_CODE (x) == PLUS
-	  && GET_CODE (XEXP (x, 1)) == CONST_INT
+	  && CONST_INT_P (XEXP (x, 1))
 	  && IN_RANGE (INTVAL (XEXP (x, 1)), -0x80, 0x80 - reach))
 	{
 	  address->offset = XEXP (x, 1);
@@ -2495,7 +2495,7 @@ legitimize_pic_address (rtx orig, machine_mode mode ATTRIBUTE_UNUSED,
       orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
 				     base == reg ? 0 : reg);
 
-      if (GET_CODE (orig) == CONST_INT)
+      if (CONST_INT_P (orig))
 	pic_ref = plus_constant (Pmode, base, INTVAL (orig));
       else
 	pic_ref = gen_rtx_PLUS (Pmode, base, orig);
@@ -2886,7 +2886,7 @@ m68k_rtx_costs (rtx x, machine_mode mode, int outer_code,
 	  && GET_CODE (XEXP (x, 1)) == REG
 	  && GET_CODE (XEXP (x, 0)) == MULT
 	  && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
-	  && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
+	  && CONST_INT_P (XEXP (XEXP (x, 0), 1))
 	  && (INTVAL (XEXP (XEXP (x, 0), 1)) == 2
 	      || INTVAL (XEXP (XEXP (x, 0), 1)) == 4
 	      || INTVAL (XEXP (XEXP (x, 0), 1)) == 8))
@@ -2907,7 +2907,7 @@ m68k_rtx_costs (rtx x, machine_mode mode, int outer_code,
 	}
       if (TUNE_68000_10)
         {
-	  if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+	  if (CONST_INT_P (XEXP (x, 1)))
 	    {
 	      if (INTVAL (XEXP (x, 1)) < 16)
 	        *total = COSTS_N_INSNS (2) + INTVAL (XEXP (x, 1)) / 2;
@@ -2920,13 +2920,13 @@ m68k_rtx_costs (rtx x, machine_mode mode, int outer_code,
 	  return true;
         }
       /* A shift by a big integer takes an extra instruction.  */
-      if (GET_CODE (XEXP (x, 1)) == CONST_INT
+      if (CONST_INT_P (XEXP (x, 1))
 	  && (INTVAL (XEXP (x, 1)) == 16))
 	{
 	  *total = COSTS_N_INSNS (2);	 /* clrw;swap */
 	  return true;
 	}
-      if (GET_CODE (XEXP (x, 1)) == CONST_INT
+      if (CONST_INT_P (XEXP (x, 1))
 	  && !(INTVAL (XEXP (x, 1)) > 0
 	       && INTVAL (XEXP (x, 1)) <= 8))
 	{
@@ -3062,7 +3062,7 @@ output_move_simode_const (rtx *operands)
 const char *
 output_move_simode (rtx *operands)
 {
-  if (GET_CODE (operands[1]) == CONST_INT)
+  if (CONST_INT_P (operands[1]))
     return output_move_simode_const (operands);
   else if ((GET_CODE (operands[1]) == SYMBOL_REF
 	    || GET_CODE (operands[1]) == CONST)
@@ -3078,7 +3078,7 @@ output_move_simode (rtx *operands)
 const char *
 output_move_himode (rtx *operands)
 {
- if (GET_CODE (operands[1]) == CONST_INT)
+ if (CONST_INT_P (operands[1]))
     {
       if (operands[1] == const0_rtx
 	  && (DATA_REG_P (operands[0])
@@ -3125,21 +3125,21 @@ output_move_qimode (rtx *operands)
       if (operands[1] == const0_rtx)
 	return "clr%.b %0";
       if ((!TARGET_COLDFIRE || DATA_REG_P (operands[0]))
-	  && GET_CODE (operands[1]) == CONST_INT
+	  && CONST_INT_P (operands[1])
 	  && (INTVAL (operands[1]) & 255) == 255)
 	{
 	  CC_STATUS_INIT;
 	  return "st %0";
 	}
     }
-  if (GET_CODE (operands[1]) == CONST_INT
+  if (CONST_INT_P (operands[1])
       && DATA_REG_P (operands[0])
       && INTVAL (operands[1]) < 128
       && INTVAL (operands[1]) >= -128)
     return "moveq %1,%0";
   if (operands[1] == const0_rtx && ADDRESS_REG_P (operands[0]))
     return "sub%.l %0,%0";
-  if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
+  if (!CONST_INT_P (operands[1]) && CONSTANT_P (operands[1]))
     return "move%.l %1,%0";
   /* 68k family (including the 5200 ColdFire) does not support byte moves to
      from address registers.  */
@@ -3176,7 +3176,7 @@ output_move_strictqi (rtx *operands)
 static const char *
 singlemove_string (rtx *operands)
 {
-  if (GET_CODE (operands[1]) == CONST_INT)
+  if (CONST_INT_P (operands[1]))
     return output_move_simode_const (operands);
   return "move%.l %1,%0";
 }
@@ -3863,7 +3863,7 @@ static void
 m68k_split_offset (rtx x, rtx *base, HOST_WIDE_INT *offset)
 {
   *offset = 0;
-  if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
+  if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
     {
       *offset += INTVAL (XEXP (x, 1));
       x = XEXP (x, 0);
@@ -4094,14 +4094,14 @@ output_addsi3 (rtx *operands)
 
       /* These insns can result from reloads to access
 	 stack slots over 64k from the frame pointer.  */
-      if (GET_CODE (operands[2]) == CONST_INT
+      if (CONST_INT_P (operands[2])
 	  && (INTVAL (operands[2]) < -32768 || INTVAL (operands[2]) > 32767))
         return "move%.l %2,%0\n\tadd%.l %1,%0";
       if (GET_CODE (operands[2]) == REG)
 	return MOTOROLA ? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
       return MOTOROLA ? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
     }
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     {
       if (INTVAL (operands[2]) > 0
 	  && INTVAL (operands[2]) <= 8)
@@ -4503,7 +4503,7 @@ print_operand (FILE *file, rtx op, int letter)
       output_address (GET_MODE (op), XEXP (op, 0));
       if (letter == 'd' && ! TARGET_68020
 	  && CONSTANT_ADDRESS_P (XEXP (op, 0))
-	  && !(GET_CODE (XEXP (op, 0)) == CONST_INT
+	  && !(CONST_INT_P (XEXP (op, 0))
 	       && INTVAL (XEXP (op, 0)) < 0x8000
 	       && INTVAL (XEXP (op, 0)) >= -0x8000))
 	fprintf (file, MOTOROLA ? ".l" : ":l");
@@ -4717,7 +4717,7 @@ print_operand_address (FILE *file, rtx addr)
     {
       /* A constant address.  */
       gcc_assert (address.offset == addr);
-      if (GET_CODE (addr) == CONST_INT)
+      if (CONST_INT_P (addr))
 	{
 	  /* (xxx).w or (xxx).l.  */
 	  if (IN_RANGE (INTVAL (addr), -0x8000, 0x7fff))
@@ -4938,7 +4938,7 @@ const char *
 output_andsi3 (rtx *operands)
 {
   int logval;
-  if (GET_CODE (operands[2]) == CONST_INT
+  if (CONST_INT_P (operands[2])
       && (INTVAL (operands[2]) | 0xffff) == -1
       && (DATA_REG_P (operands[0])
 	  || offsettable_memref_p (operands[0]))
@@ -4953,7 +4953,7 @@ output_andsi3 (rtx *operands)
         return "clr%.w %0";
       return "and%.w %2,%0";
     }
-  if (GET_CODE (operands[2]) == CONST_INT
+  if (CONST_INT_P (operands[2])
       && (logval = exact_log2 (~ INTVAL (operands[2]) & 0xffffffff)) >= 0
       && (DATA_REG_P (operands[0])
           || offsettable_memref_p (operands[0])))
@@ -4976,7 +4976,7 @@ const char *
 output_iorsi3 (rtx *operands)
 {
   register int logval;
-  if (GET_CODE (operands[2]) == CONST_INT
+  if (CONST_INT_P (operands[2])
       && INTVAL (operands[2]) >> 16 == 0
       && (DATA_REG_P (operands[0])
 	  || offsettable_memref_p (operands[0]))
@@ -4990,7 +4990,7 @@ output_iorsi3 (rtx *operands)
 	return "mov%.w %2,%0";
       return "or%.w %2,%0";
     }
-  if (GET_CODE (operands[2]) == CONST_INT
+  if (CONST_INT_P (operands[2])
       && (logval = exact_log2 (INTVAL (operands[2]) & 0xffffffff)) >= 0
       && (DATA_REG_P (operands[0])
 	  || offsettable_memref_p (operands[0])))
@@ -5012,7 +5012,7 @@ const char *
 output_xorsi3 (rtx *operands)
 {
   register int logval;
-  if (GET_CODE (operands[2]) == CONST_INT
+  if (CONST_INT_P (operands[2])
       && INTVAL (operands[2]) >> 16 == 0
       && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0]))
       && !TARGET_COLDFIRE)
@@ -5025,7 +5025,7 @@ output_xorsi3 (rtx *operands)
 	return "not%.w %0";
       return "eor%.w %2,%0";
     }
-  if (GET_CODE (operands[2]) == CONST_INT
+  if (CONST_INT_P (operands[2])
       && (logval = exact_log2 (INTVAL (operands[2]) & 0xffffffff)) >= 0
       && (DATA_REG_P (operands[0])
 	  || offsettable_memref_p (operands[0])))
@@ -5287,7 +5287,7 @@ m68k_preferred_reload_class (rtx x, enum reg_class rclass)
     return secondary_class;
 
   /* Prefer to use moveq for in-range constants.  */
-  if (GET_CODE (x) == CONST_INT
+  if (CONST_INT_P (x)
       && reg_class_subset_p (DATA_REGS, rclass)
       && IN_RANGE (INTVAL (x), -0x80, 0x7f))
     return DATA_REGS;
@@ -5522,7 +5522,7 @@ sched_attr_op_type (rtx_insn *insn, bool opx_p, bool address_p)
       return OP_TYPE_RN;
     }
 
-  if (GET_CODE (op) == CONST_INT)
+  if (CONST_INT_P (op))
     {
       int ival;
 
diff --git a/gcc/config/m68k/m68k.h b/gcc/config/m68k/m68k.h
index fc65e524b13..4f7adbff060 100644
--- a/gcc/config/m68k/m68k.h
+++ b/gcc/config/m68k/m68k.h
@@ -631,7 +631,7 @@ __transfer_from_trampoline ()					\
 
 #define CONSTANT_ADDRESS_P(X)						\
   ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
-    || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST		\
+    || CONST_INT_P (X) || GET_CODE (X) == CONST		\
     || GET_CODE (X) == HIGH)						\
    && m68k_legitimate_constant_p (Pmode, X))
 
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index 31e8767e7e3..d3c41028fae 100644
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -513,7 +513,7 @@
       return "cmp%.l %d0,%d1";
     }
   if (ADDRESS_REG_P (operands[0])
-      && GET_CODE (operands[1]) == CONST_INT
+      && CONST_INT_P (operands[1])
       && INTVAL (operands[1]) < 0x8000
       && INTVAL (operands[1]) >= -0x8000)
     return "cmp%.w %1,%0";
@@ -1601,7 +1601,7 @@
 {
   if (GET_CODE (operands[0]) == REG
       && (GET_CODE (operands[1]) == MEM
-	  || GET_CODE (operands[1]) == CONST_INT))
+	  || CONST_INT_P (operands[1])))
     {
       /* Must clear condition codes, since the move.w bases them on
 	 the entire 16 bits, not just the desired 8 bits.  */
@@ -1885,7 +1885,7 @@
 {
   CC_STATUS_INIT;
   operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  if (GET_CODE (operands[1]) == CONST_INT
+  if (CONST_INT_P (operands[1])
   && (unsigned) INTVAL (operands[1]) > 8)
     {
       rtx tmp = operands[1];
@@ -2389,14 +2389,14 @@
 
 	  operands[1] = low, operands[2] = high;
 	  xoperands[0] = operands[3];
-	  if (GET_CODE (operands[1]) == CONST_INT
+	  if (CONST_INT_P (operands[1])
 	      && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
 	    xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
 	  else
 	    xoperands[1] = operands[2];
 
 	  output_asm_insn (output_move_simode (xoperands), xoperands);
-	  if (GET_CODE (operands[1]) == CONST_INT)
+	  if (CONST_INT_P (operands[1]))
 	    {
 	      if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
 		return "addq%.l %1,%R0\;addx%.l %3,%0";
@@ -2541,7 +2541,7 @@
 		 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
   "!TARGET_COLDFIRE"
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     {
       /* If the constant would be a negative number when interpreted as
 	 HImode, make it negative.  This is usually, but not always, done
@@ -2596,7 +2596,7 @@
 		 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
   "!TARGET_COLDFIRE"
 {
-  if (GET_CODE (operands[1]) == CONST_INT)
+  if (CONST_INT_P (operands[1]))
     {
       /* If the constant would be a negative number when interpreted as
 	 HImode, make it negative.  This is usually, but not always, done
@@ -2645,7 +2645,7 @@
 		 (match_dup 0)))]
   "!TARGET_COLDFIRE"
 {
-  if (GET_CODE (operands[1]) == CONST_INT)
+  if (CONST_INT_P (operands[1]))
     {
       /* If the constant would be a negative number when interpreted as
 	 HImode, make it negative.  This is usually, but not always, done
@@ -2694,7 +2694,7 @@
 		 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
   "!TARGET_COLDFIRE"
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     {
       if (INTVAL (operands[2]) >= 128)
 	operands[2] = GEN_INT (INTVAL (operands[2]) - 256);
@@ -2717,7 +2717,7 @@
 		 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
   "!TARGET_COLDFIRE"
 {
-  if (GET_CODE (operands[1]) == CONST_INT)
+  if (CONST_INT_P (operands[1]))
     {
       if (INTVAL (operands[1]) >= 128)
 	operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
@@ -2740,7 +2740,7 @@
 		 (match_dup 0)))]
   "!TARGET_COLDFIRE"
 {
-  if (GET_CODE (operands[1]) == CONST_INT)
+  if (CONST_INT_P (operands[1]))
     {
       if (INTVAL (operands[1]) >= 128)
 	operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
@@ -2888,14 +2888,14 @@
 
 	  operands[1] = low, operands[2] = high;
 	  xoperands[0] = operands[3];
-	  if (GET_CODE (operands[1]) == CONST_INT
+	  if (CONST_INT_P (operands[1])
 	      && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
 	    xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
 	  else
 	    xoperands[1] = operands[2];
 
 	  output_asm_insn (output_move_simode (xoperands), xoperands);
-	  if (GET_CODE (operands[1]) == CONST_INT)
+	  if (CONST_INT_P (operands[1]))
 	    {
 	      if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
 		return "subq%.l %1,%R0\;subx%.l %3,%0";
@@ -3219,7 +3219,7 @@
 {
   operands[3] = gen_reg_rtx (SImode);
 
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     {
       operands[2] = immed_double_const (INTVAL (operands[2]) & 0xffffffff,
 					0, DImode);
@@ -3271,7 +3271,7 @@
   "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
 {
   operands[3] = gen_reg_rtx (SImode);
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     {
       /* We have to adjust the operand order for the matching constraints.  */
       emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
@@ -3654,7 +3654,7 @@
 {
   if (ISA_HAS_MVS_MVZ
       && DATA_REG_P (operands[0])
-      && GET_CODE (operands[2]) == CONST_INT)
+      && CONST_INT_P (operands[2]))
     {
       if (INTVAL (operands[2]) == 0x000000ff)
         return "mvz%.b %0,%0";
@@ -4563,7 +4563,7 @@
 {
   /* ???  This is a named pattern like this is not allowed to FAIL based
      on its operands.  */
-  if (GET_CODE (operands[2]) != CONST_INT
+  if (!CONST_INT_P (operands[2])
       || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
 	  && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
 	  && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
@@ -4833,7 +4833,7 @@
 {
   /* ???  This is a named pattern like this is not allowed to FAIL based
      on its operands.  */
-  if (GET_CODE (operands[2]) != CONST_INT
+  if (!CONST_INT_P (operands[2])
       || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
 	  && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
 	  && (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63)))
@@ -5105,7 +5105,7 @@
 {
   /* ???  This is a named pattern like this is not allowed to FAIL based
      on its operands.  */
-  if (GET_CODE (operands[2]) != CONST_INT
+  if (!CONST_INT_P (operands[2])
       || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
 	  && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
 	  && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
@@ -5203,9 +5203,9 @@
 		   (match_operand:SI 2 "general_operand" "dINO")))]
   "!TARGET_COLDFIRE"
 {
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
+  if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 16)
     return "swap %0";
-  else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
+  else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) >= 16)
     {
       operands[2] = GEN_INT (32 - INTVAL (operands[2]));
       return "ror%.l %2,%0";
@@ -5220,7 +5220,7 @@
 		   (match_operand:HI 2 "general_operand" "dIP")))]
   "!TARGET_COLDFIRE"
 {
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
+  if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) >= 8)
     {
       operands[2] = GEN_INT (16 - INTVAL (operands[2]));
       return "ror%.w %2,%0";
@@ -5235,7 +5235,7 @@
 		   (match_operand:HI 1 "general_operand" "dIP")))]
   "!TARGET_COLDFIRE"
 {
-  if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) >= 8)
+  if (CONST_INT_P (operands[1]) && INTVAL (operands[1]) >= 8)
     {
       operands[1] = GEN_INT (16 - INTVAL (operands[1]));
       return "ror%.w %1,%0";
@@ -5250,7 +5250,7 @@
 		   (match_operand:QI 2 "general_operand" "dI")))]
   "!TARGET_COLDFIRE"
 {
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
+  if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) >= 4)
     {
       operands[2] = GEN_INT (8 - INTVAL (operands[2]));
       return "ror%.b %2,%0";
@@ -5265,7 +5265,7 @@
 		   (match_operand:QI 1 "general_operand" "dI")))]
   "!TARGET_COLDFIRE"
 {
-  if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) >= 4)
+  if (CONST_INT_P (operands[1]) && INTVAL (operands[1]) >= 4)
     {
       operands[1] = GEN_INT (8 - INTVAL (operands[1]));
       return "ror%.b %1,%0";
@@ -5586,7 +5586,7 @@
 			 (match_operand:SI 3 "nonmemory_operand" "dn")))]
   "TARGET_68020 && TARGET_BITFIELD"
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     {
       if (INTVAL (operands[2]) != 32)
 	cc_status.flags |= CC_NOT_NEGATIVE;
@@ -5606,7 +5606,7 @@
 		(match_operand 3 "const_int_operand" "n")))]
   "TARGET_68020 && TARGET_BITFIELD
    && (INTVAL (operands[3]) == -1
-       || (GET_CODE (operands[1]) == CONST_INT
+       || (CONST_INT_P (operands[1])
            && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
 {
   CC_STATUS_INIT;
@@ -5644,7 +5644,7 @@
   "
 {
   /* Special case initializing a field to all ones. */
-  if (GET_CODE (operands[3]) == CONST_INT)
+  if (CONST_INT_P (operands[3]))
     {
       if (exact_log2 (INTVAL (operands[3]) + 1) != INTVAL (operands[1]))
 	operands[3] = force_reg (SImode, operands[3]);
@@ -5680,7 +5680,7 @@
 			 (match_operand:SI 3 "const_int_operand" "n")))]
   "TARGET_68020 && TARGET_BITFIELD && IN_RANGE (INTVAL (operands[3]), 0, 31)"
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     {
       if (INTVAL (operands[2]) != 32)
 	cc_status.flags |= CC_NOT_NEGATIVE;
@@ -5723,10 +5723,10 @@
 {
 #if 0
   /* These special cases are now recognized by a specific pattern.  */
-  if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
+  if (CONST_INT_P (operands[1]) && CONST_INT_P (operands[2])
       && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
     return "move%.w %3,%0";
-  if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
+  if (CONST_INT_P (operands[1]) && CONST_INT_P (operands[2])
       && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
     return "move%.b %3,%0";
 #endif
@@ -5744,7 +5744,7 @@
   "TARGET_68020 && TARGET_BITFIELD"
 {
   if (operands[1] == const1_rtx
-      && GET_CODE (operands[2]) == CONST_INT)
+      && CONST_INT_P (operands[2]))
     {
       int width = GET_CODE (operands[0]) == REG ? 31 : 7;
       return output_btst (operands,
@@ -5771,7 +5771,7 @@
     && !(CONST_INT_P (operands[2]) && !IN_RANGE (INTVAL (operands[2]), 0, 31))"
 {
   if (operands[1] == const1_rtx
-      && GET_CODE (operands[2]) == CONST_INT)
+      && CONST_INT_P (operands[2]))
     {
       int width = GET_CODE (operands[0]) == REG ? 31 : 7;
       return output_btst (operands, GEN_INT (width - INTVAL (operands[2])),
diff --git a/gcc/config/m68k/predicates.md b/gcc/config/m68k/predicates.md
index ad297883f85..efda85872d1 100644
--- a/gcc/config/m68k/predicates.md
+++ b/gcc/config/m68k/predicates.md
@@ -91,10 +91,10 @@
 
 #if HOST_BITS_PER_WIDE_INT > 32
   /* All allowed constants will fit a CONST_INT.  */
-  return (GET_CODE (op) == CONST_INT
+  return (CONST_INT_P (op)
 	  && (INTVAL (op) >= 0 && INTVAL (op) <= 0xffffffffL));
 #else
-  return (GET_CODE (op) == CONST_INT
+  return (CONST_INT_P (op)
 	  || (GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_HIGH (op) == 0));
 #endif
 })
@@ -111,7 +111,7 @@
   gcc_assert (GET_MODE_BITSIZE (mode) > 32);
 
   /* All allowed constants will fit a CONST_INT.  */
-  return (GET_CODE (op) == CONST_INT
+  return (CONST_INT_P (op)
 	  && (INTVAL (op) >= (-0x7fffffff - 1) && INTVAL (op) <= 0x7fffffff));
 })
 
@@ -152,7 +152,7 @@
       op = XEXP (op, 0);
       return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
 	       || GET_CODE (XEXP (op, 0)) == LABEL_REF)
-	      && GET_CODE (XEXP (op, 1)) == CONST_INT);
+	      && CONST_INT_P (XEXP (op, 1)));
 
 #if 0 /* Deleted, with corresponding change in m68k.h,
 	 so as to fit the specs.  No CONST_DOUBLE is ever symbolic.  */
@@ -272,7 +272,7 @@
 (define_predicate "pow2_m1_operand"
   (match_code "const_int")
 {
-  return (GET_CODE (op) == CONST_INT && exact_log2 (INTVAL (op) + 1) >= 0);
+  return (CONST_INT_P (op) && exact_log2 (INTVAL (op) + 1) >= 0);
 })
 
 ;; Used to detect valid targets for conditional branches
diff --git a/gcc/config/mcore/mcore.c b/gcc/config/mcore/mcore.c
index 06f093eee12..8c249ab2b61 100644
--- a/gcc/config/mcore/mcore.c
+++ b/gcc/config/mcore/mcore.c
@@ -491,7 +491,7 @@ mcore_and_cost (rtx x)
 {
   HOST_WIDE_INT val;
 
-  if (GET_CODE (XEXP (x, 1)) != CONST_INT)
+  if (!CONST_INT_P (XEXP (x, 1)))
     return 2;
 
   val = INTVAL (XEXP (x, 1));
@@ -517,7 +517,7 @@ mcore_ior_cost (rtx x)
 {
   HOST_WIDE_INT val;
 
-  if (GET_CODE (XEXP (x, 1)) != CONST_INT)
+  if (!CONST_INT_P (XEXP (x, 1)))
     return 2;
 
   val = INTVAL (XEXP (x, 1));
@@ -588,7 +588,7 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1)
   rtx cc_reg = gen_rtx_REG (CCmode, CC_REG);
   bool invert;
 
-  if (GET_CODE (op1) == CONST_INT)
+  if (CONST_INT_P (op1))
     {
       HOST_WIDE_INT val = INTVAL (op1);
       
@@ -617,7 +617,7 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1)
 	}
     }
  
-  if (CONSTANT_P (op1) && GET_CODE (op1) != CONST_INT)
+  if (CONSTANT_P (op1) && !CONST_INT_P (op1))
     op1 = force_reg (SImode, op1);
 
   /* cmpnei: 0-31 (K immediate)
@@ -631,7 +631,7 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1)
       /* FALLTHRU */
       
     case NE:	/* Use normal condition, cmpne.  */
-      if (GET_CODE (op1) == CONST_INT && ! CONST_OK_FOR_K (INTVAL (op1)))
+      if (CONST_INT_P (op1) && ! CONST_OK_FOR_K (INTVAL (op1)))
 	op1 = force_reg (SImode, op1);
       break;
 
@@ -641,7 +641,7 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1)
       /* FALLTHRU */
       
     case GT:	/* Use normal condition, reversed cmplt.  */
-      if (GET_CODE (op1) == CONST_INT)
+      if (CONST_INT_P (op1))
 	op1 = force_reg (SImode, op1);
       break;
 
@@ -651,7 +651,7 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1)
       /* FALLTHRU */
       
     case LT:	/* Use normal condition, cmplt.  */
-      if (GET_CODE (op1) == CONST_INT && 
+      if (CONST_INT_P (op1) && 
 	  /* covered by btsti x,31.  */
 	  INTVAL (op1) != 0 &&
 	  ! CONST_OK_FOR_J (INTVAL (op1)))
@@ -660,13 +660,13 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1)
 
     case GTU:	/* Use inverted condition, cmple.  */
       /* We coped with unsigned > 0 above.  */
-      gcc_assert (GET_CODE (op1) != CONST_INT || INTVAL (op1) != 0);
+      gcc_assert (!CONST_INT_P (op1) || INTVAL (op1) != 0);
       code = LEU;
       invert = true;
       /* FALLTHRU */
       
     case LEU:	/* Use normal condition, reversed cmphs.  */
-      if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0)
+      if (CONST_INT_P (op1) && INTVAL (op1) != 0)
 	op1 = force_reg (SImode, op1);
       break;
 
@@ -676,7 +676,7 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1)
       /* FALLTHRU */
       
     case GEU:	/* Use normal condition, cmphs.  */
-      if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0)
+      if (CONST_INT_P (op1) && INTVAL (op1) != 0)
 	op1 = force_reg (SImode, op1);
       break;
 
@@ -700,7 +700,7 @@ mcore_symbolic_address_p (rtx x)
       x = XEXP (x, 0);
       return (   (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
 	       || GET_CODE (XEXP (x, 0)) == LABEL_REF)
-	      && GET_CODE (XEXP (x, 1)) == CONST_INT);
+	      && CONST_INT_P (XEXP (x, 1)));
     default:
       return 0;
     }
@@ -1308,7 +1308,7 @@ mcore_output_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
 		gcc_unreachable ();
 	      }
 	}
-      else if (GET_CODE (src) == CONST_INT)
+      else if (CONST_INT_P (src))
 	{
 	  HOST_WIDE_INT x, y;
 	  
@@ -1399,7 +1399,7 @@ mcore_output_movedouble (rtx operands[], machine_mode mode ATTRIBUTE_UNUSED)
 	  else
 	    return "ldw\t%0,%1\n\tldw\t%R0,%R1";
 	}
-      else if (GET_CODE (src) == CONST_INT)
+      else if (CONST_INT_P (src))
 	{
 	  if (TARGET_LITTLE_END)
 	    {
@@ -1448,7 +1448,7 @@ mcore_output_movedouble (rtx operands[], machine_mode mode ATTRIBUTE_UNUSED)
 int
 mcore_arith_S_operand (rtx op)
 {
-  if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (~INTVAL (op)))
+  if (CONST_INT_P (op) && CONST_OK_FOR_M (~INTVAL (op)))
     return 1;
   
   return 0;
@@ -1467,7 +1467,7 @@ mcore_expand_insv (rtx operands[])
   /* To get width 1 insv, the test in store_bit_field() (expmed.c, line 191)
      for width==1 must be removed.  Look around line 368.  This is something
      we really want the md part to do.  */
-  if (width == 1 && GET_CODE (operands[3]) == CONST_INT)
+  if (width == 1 && CONST_INT_P (operands[3]))
     {
       /* Do directly with bseti or bclri.  */
       /* RBE: 2/97 consider only low bit of constant.  */
@@ -1508,7 +1508,7 @@ mcore_expand_insv (rtx operands[])
      immediates.  */
 
   /* If setting the entire field, do it directly.  */
-  if (GET_CODE (operands[3]) == CONST_INT
+  if (CONST_INT_P (operands[3])
       && INTVAL (operands[3]) == ((1 << width) - 1))
     {
       mreg = force_reg (SImode, GEN_INT (INTVAL (operands[3]) << posn));
@@ -1525,7 +1525,7 @@ mcore_expand_insv (rtx operands[])
 			  gen_rtx_AND (SImode, operands[0], mreg)));
 
   /* If the source is constant 0, we've nothing to add back.  */
-  if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) == 0)
+  if (CONST_INT_P (operands[3]) && INTVAL (operands[3]) == 0)
     return 1;
 
   /* XXX: Should we worry about more games with constant values?
@@ -1646,7 +1646,7 @@ mcore_expand_block_move (rtx *operands)
 {
   HOST_WIDE_INT align, bytes, max;
 
-  if (GET_CODE (operands[2]) != CONST_INT)
+  if (!CONST_INT_P (operands[2]))
     return false;
 
   bytes = INTVAL (operands[2]);
@@ -2303,7 +2303,7 @@ is_cond_candidate (rtx insn)
 	    GET_CODE (SUBREG_REG (src)) == REG)) &&
 	  GET_MODE (src) == SImode)
 	return COND_MOV_INSN;
-      else if (GET_CODE (src) == CONST_INT && 
+      else if (CONST_INT_P (src) && 
                INTVAL (src) == 0)
 	return COND_CLR_INSN;
       else if (GET_CODE (src) == PLUS &&
@@ -2311,14 +2311,14 @@ is_cond_candidate (rtx insn)
                 (GET_CODE (XEXP (src, 0)) == SUBREG &&
                  GET_CODE (SUBREG_REG (XEXP (src, 0))) == REG)) &&
                GET_MODE (XEXP (src, 0)) == SImode &&
-               GET_CODE (XEXP (src, 1)) == CONST_INT &&
+               CONST_INT_P (XEXP (src, 1)) &&
                INTVAL (XEXP (src, 1)) == 1)
 	return COND_INC_INSN;
       else if (((GET_CODE (src) == MINUS &&
-		 GET_CODE (XEXP (src, 1)) == CONST_INT &&
+		 CONST_INT_P (XEXP (src, 1)) &&
 		 INTVAL( XEXP (src, 1)) == 1) ||
                 (GET_CODE (src) == PLUS &&
-		 GET_CODE (XEXP (src, 1)) == CONST_INT &&
+		 CONST_INT_P (XEXP (src, 1)) &&
 		 INTVAL (XEXP (src, 1)) == -1)) &&
                (GET_CODE (XEXP (src, 0)) == REG ||
 		(GET_CODE (XEXP (src, 0)) == SUBREG &&
diff --git a/gcc/config/mcore/mcore.md b/gcc/config/mcore/mcore.md
index c6893518dc0..71f0bc0b17c 100644
--- a/gcc/config/mcore/mcore.md
+++ b/gcc/config/mcore/mcore.md
@@ -335,7 +335,7 @@
   ""
   "
 {
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0
+  if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0
       && ! mcore_arith_S_operand (operands[2]))
     {
       HOST_WIDE_INT not_value = ~ INTVAL (operands[2]);
@@ -537,7 +537,7 @@
 ;  ""
 ;  "
 ;{
-;  if (GET_CODE (operands[2]) != CONST_INT
+;  if (!CONST_INT_P (operands[2])
 ;      || INTVAL (operands[2]) != 1)
 ;    FAIL;
 ;}")
@@ -685,7 +685,7 @@
   /* Convert adds to subtracts if this makes loading the constant cheaper.
      But only if we are allowed to generate new pseudos.  */
   if (! (reload_in_progress || reload_completed)
-      && GET_CODE (operands[2]) == CONST_INT
+      && CONST_INT_P (operands[2])
       && INTVAL (operands[2]) < -32)
     {
       HOST_WIDE_INT neg_value = - INTVAL (operands[2]);
@@ -716,7 +716,7 @@
 ;;   [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
 ;;      (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0")
 ;;               (match_operand:SI 2 "const_int_operand" "g")))]
-;;   "GET_CODE(operands[2]) == CONST_INT
+;;   "CONST_INT_P (operands[2])
 ;;    && ((INTVAL (operands[2]) > 32 && INTVAL(operands[2]) <= 64)
 ;;        || (INTVAL (operands[2]) < -32 && INTVAL(operands[2]) >= -64))"
 ;;   "*
@@ -774,7 +774,7 @@
 ;;   [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
 ;;      (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0")
 ;;               (match_operand:SI 2 "const_int_operand" "g")))]
-;;   "TARGET_RBETEST && GET_CODE(operands[2]) == CONST_INT
+;;   "TARGET_RBETEST && CONST_INT_P (operands[2])
 ;;    && ((INTVAL (operands[2]) > 32 && INTVAL(operands[2]) <= 64)
 ;;        || (INTVAL (operands[2]) < -32 && INTVAL(operands[2]) >= -64))"
 ;;   "*
@@ -881,7 +881,7 @@
 	(plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")
 		 (match_operand:SI 2 "const_int_operand" "r")))
    (clobber (reg:CC 17))]
-  "GET_CODE (operands[2]) == CONST_INT
+  "CONST_INT_P (operands[2])
    && INTVAL (operands[2]) > 0 && ! (INTVAL (operands[2]) & 0x80000000)"
   "*
 {
@@ -1210,7 +1210,7 @@
   if (GET_CODE (operands[0]) == MEM)
     operands[1] = force_reg (HImode, operands[1]);
   else if (CONSTANT_P (operands[1])
-	   && (GET_CODE (operands[1]) != CONST_INT
+	   && (!CONST_INT_P (operands[1])
 	       || (! CONST_OK_FOR_I (INTVAL (operands[1]))
 		   && ! CONST_OK_FOR_M (INTVAL (operands[1]))
 		   && ! CONST_OK_FOR_N (INTVAL (operands[1]))))
@@ -1243,7 +1243,7 @@
   if (GET_CODE (operands[0]) == MEM)
     operands[1] = force_reg (QImode, operands[1]);
   else if (CONSTANT_P (operands[1])
-	   && (GET_CODE (operands[1]) != CONST_INT
+	   && (!CONST_INT_P (operands[1])
 	       || (! CONST_OK_FOR_I (INTVAL (operands[1]))
 		   && ! CONST_OK_FOR_M (INTVAL (operands[1]))
 		   && ! CONST_OK_FOR_N (INTVAL (operands[1]))))
@@ -1274,7 +1274,7 @@
 {
   if (GET_CODE (operands[0]) == MEM)
     operands[1] = force_reg (DImode, operands[1]);
-  else if (GET_CODE (operands[1]) == CONST_INT
+  else if (CONST_INT_P (operands[1])
            && ! CONST_OK_FOR_I (INTVAL (operands[1]))
 	   && ! CONST_OK_FOR_M (INTVAL (operands[1]))
 	   && ! CONST_OK_FOR_N (INTVAL (operands[1])))
@@ -1363,7 +1363,7 @@
 
   /* Support only loading a constant number of registers from memory and
      only if at least two registers.  The last register must be r15.  */
-  if (GET_CODE (operands[2]) != CONST_INT
+  if (!CONST_INT_P (operands[2])
       || INTVAL (operands[2]) < 2
       || GET_CODE (operands[1]) != MEM
       || XEXP (operands[1], 0) != stack_pointer_rtx
@@ -1401,7 +1401,7 @@
 
   /* Support only storing a constant number of registers to memory and
      only if at least two registers.  The last register must be r15.  */
-  if (GET_CODE (operands[2]) != CONST_INT
+  if (!CONST_INT_P (operands[2])
       || INTVAL (operands[2]) < 2
       || GET_CODE (operands[0]) != MEM
       || XEXP (operands[0], 0) != stack_pointer_rtx
@@ -1855,8 +1855,8 @@
             (ne (reg:CC 17) (const_int 0))
           (match_operand:SI 1 "mcore_arith_O_operand" "O")
           (match_operand:SI 2 "mcore_arith_O_operand" "O")))]
-  "  GET_CODE (operands[1]) == CONST_INT
-  && GET_CODE (operands[2]) == CONST_INT
+  "  CONST_INT_P (operands[1])
+  && CONST_INT_P (operands[2])
   && (   (INTVAL (operands[1]) - INTVAL (operands[2]) == 1)
       || (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
   "* return mcore_output_cmov (operands, 1, NULL);"
@@ -1886,8 +1886,8 @@
             (eq (reg:CC 17) (const_int 0))
           (match_operand:SI 1 "mcore_arith_O_operand" "O")
           (match_operand:SI 2 "mcore_arith_O_operand" "O")))]
-  "  GET_CODE (operands[1]) == CONST_INT
-  && GET_CODE (operands[2]) == CONST_INT
+  "  CONST_INT_P (operands[1])
+  && CONST_INT_P (operands[2])
   && (   (INTVAL (operands[1]) - INTVAL (operands[2]) == 1)
       || (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
   "* return mcore_output_cmov (operands, 0, NULL);"
@@ -1962,8 +1962,8 @@
                 (const_int 0))
           (match_operand:SI 2 "mcore_arith_O_operand" "O")
           (match_operand:SI 3 "mcore_arith_O_operand" "O")))]
-  "  GET_CODE (operands[2]) == CONST_INT
-  && GET_CODE (operands[3]) == CONST_INT
+  "  CONST_INT_P (operands[2])
+  && CONST_INT_P (operands[3])
   && (   (INTVAL (operands[2]) - INTVAL (operands[3]) == 1)
       || (INTVAL (operands[3]) - INTVAL (operands[2]) == 1))"
   "*
@@ -2044,8 +2044,8 @@
             (eq (eq:SI (reg:CC 17) (const_int 0)) (const_int 0))
           (match_operand:SI 1 "mcore_arith_O_operand" "O")
           (match_operand:SI 2 "mcore_arith_O_operand" "O")))]
-  "GET_CODE (operands[1]) == CONST_INT &&
-   GET_CODE (operands[2]) == CONST_INT &&
+  "CONST_INT_P (operands[1]) &&
+   CONST_INT_P (operands[2]) &&
    ((INTVAL (operands[1]) - INTVAL (operands[2]) == 1) ||
    (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
   "* return mcore_output_cmov(operands, 1, NULL);"
@@ -2075,8 +2075,8 @@
             (eq (ne:SI (reg:CC 17) (const_int 0)) (const_int 0))
           (match_operand:SI 1 "mcore_arith_O_operand" "O")
           (match_operand:SI 2 "mcore_arith_O_operand" "O")))]
-  "GET_CODE (operands[1]) == CONST_INT &&
-   GET_CODE (operands[2]) == CONST_INT &&
+  "CONST_INT_P (operands[1]) &&
+   CONST_INT_P (operands[2]) &&
    ((INTVAL (operands[1]) - INTVAL (operands[2]) == 1) ||
     (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
   "* return mcore_output_cmov (operands, 0, NULL);"
@@ -2111,8 +2111,8 @@
                 (const_int 0))
           (match_operand:SI 2 "mcore_arith_O_operand" "O")
           (match_operand:SI 3 "mcore_arith_O_operand" "O")))]
-  "GET_CODE (operands[1]) == CONST_INT &&
-   GET_CODE (operands[2]) == CONST_INT &&
+  "CONST_INT_P (operands[1]) &&
+   CONST_INT_P (operands[2]) &&
    ((INTVAL (operands[2]) - INTVAL (operands[3]) == 1) ||
     (INTVAL (operands[3]) - INTVAL (operands[2]) == 1))"
   "* 
@@ -2152,8 +2152,8 @@
             (ne (eq:SI (reg:CC 17) (const_int 0)) (const_int 0))
           (match_operand:SI 1 "mcore_arith_O_operand" "O")
           (match_operand:SI 2 "mcore_arith_O_operand" "O")))]
-  "GET_CODE (operands[1]) == CONST_INT &&
-   GET_CODE (operands[2]) == CONST_INT &&
+  "CONST_INT_P (operands[1]) &&
+   CONST_INT_P (operands[2]) &&
    ((INTVAL (operands[1]) - INTVAL (operands[2]) == 1) ||
     (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
   "* return mcore_output_cmov (operands, 0, NULL);"
@@ -2183,8 +2183,8 @@
             (ne (ne:SI (reg:CC 17) (const_int 0)) (const_int 0))
           (match_operand:SI 1 "mcore_arith_O_operand" "O")
           (match_operand:SI 2 "mcore_arith_O_operand" "O")))]
-  "GET_CODE (operands[1]) == CONST_INT &&
-   GET_CODE (operands[2]) == CONST_INT &&
+  "CONST_INT_P (operands[1]) &&
+   CONST_INT_P (operands[2]) &&
    ((INTVAL (operands[1]) - INTVAL (operands[2]) == 1) ||
     (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
   "* return mcore_output_cmov (operands, 1, NULL);"
@@ -2218,8 +2218,8 @@
                 (const_int 0))
           (match_operand:SI 2 "mcore_arith_O_operand" "O")
           (match_operand:SI 3 "mcore_arith_O_operand" "O")))]
-  "GET_CODE (operands[2]) == CONST_INT &&
-   GET_CODE (operands[3]) == CONST_INT &&
+  "CONST_INT_P (operands[2]) &&
+   CONST_INT_P (operands[3]) &&
    ((INTVAL (operands[2]) - INTVAL (operands[3]) == 1) ||
     (INTVAL (operands[3]) - INTVAL (operands[2]) == 1))"
   "*
@@ -2261,8 +2261,8 @@
                 (const_int 0))
           (match_operand:SI 2 "mcore_arith_O_operand" "O")
           (match_operand:SI 3 "mcore_arith_O_operand" "O")))]
-  "GET_CODE (operands[2]) == CONST_INT &&
-   GET_CODE (operands[3]) == CONST_INT &&
+  "CONST_INT_P (operands[2]) &&
+   CONST_INT_P (operands[3]) &&
    ((INTVAL (operands[2]) - INTVAL (operands[3]) == 1) ||
     (INTVAL (operands[3]) - INTVAL (operands[2]) == 1))"
   "*
@@ -2623,7 +2623,7 @@
       (set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
 	   (match_operand:SI 1 "mcore_arith_reg_operand" "+r"))
       (set (match_dup 1) (plus:SI (match_dup 1) (match_operand 2 "mcore_arith_any_imm_operand" "")))])]
-  "GET_CODE(operands[2]) == CONST_INT"
+  "CONST_INT_P (operands[2])"
   "#"
   [(set_attr "length" "4")])
 
@@ -2632,7 +2632,7 @@
       (set (match_operand:SI 0 "mcore_arith_reg_operand" "")
 	   (match_operand:SI 1 "mcore_arith_reg_operand" ""))
       (set (match_dup 1) (plus:SI (match_dup 1) (match_operand 2 "mcore_arith_any_imm_operand" "")))])]
-  "GET_CODE(operands[2]) == CONST_INT &&
+  "CONST_INT_P (operands[2]) &&
    operands[0] != operands[1]"
   [(set (match_dup 0) (match_dup 1))
    (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))])
@@ -2841,7 +2841,7 @@
 
   if (GET_CODE (operands[3]) == REG)
     {
-     if (REGNO (operands[3]) == op0 && GET_CODE (operands[4]) == CONST_INT
+     if (REGNO (operands[3]) == op0 && CONST_INT_P (operands[4])
 	 && INTVAL (operands[4]) == 0)
         return \"btsti	%1,%2\\n\\tclrf	%0\";
      else if (GET_CODE (operands[4]) == REG)
@@ -2854,7 +2854,7 @@
 
      gcc_unreachable ();
     }
-  else if (GET_CODE (operands[3]) == CONST_INT
+  else if (CONST_INT_P (operands[3])
            && INTVAL (operands[3]) == 0
 	   && GET_CODE (operands[4]) == REG)
      return \"btsti	%1,%2\\n\\tclrt	%0\";
@@ -2978,7 +2978,7 @@
     }
 
   /* For small constant growth, we unroll the code.  */
-  if (GET_CODE (operands[1]) == CONST_INT
+  if (CONST_INT_P (operands[1])
       && INTVAL (operands[1]) < 8 * STACK_UNITS_MAXSTEP)
     {
       HOST_WIDE_INT left = INTVAL(operands[1]);
@@ -3016,7 +3016,7 @@
       emit_insn (gen_movsi (tmp, operands[1]));
       emit_insn (gen_movsi (step, GEN_INT (STACK_UNITS_MAXSTEP)));
 
-      if (GET_CODE (operands[1]) != CONST_INT)
+      if (!CONST_INT_P (operands[1]))
 	{
 	  out_label = gen_label_rtx ();
 	  test = gen_rtx_GEU (VOIDmode, step, tmp);		/* quick out */
diff --git a/gcc/config/mcore/predicates.md b/gcc/config/mcore/predicates.md
index baf0e20acdc..344a1e0b14e 100644
--- a/gcc/config/mcore/predicates.md
+++ b/gcc/config/mcore/predicates.md
@@ -80,7 +80,7 @@
   if (register_operand (op, mode))
     return 1;
 
-  if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_J (INTVAL (op)))
+  if (CONST_INT_P (op) && CONST_OK_FOR_J (INTVAL (op)))
     return 1;
 
   return 0;
@@ -94,7 +94,7 @@
   if (register_operand (op, mode))
     return 1;
 
-  if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
+  if (CONST_INT_P (op) && CONST_OK_FOR_K (INTVAL (op)))
     return 1;
 
   return 0;
@@ -108,7 +108,7 @@
   if (register_operand (op, mode))
     return 1;
 
-  if (   GET_CODE (op) == CONST_INT
+  if (   CONST_INT_P (op)
       && CONST_OK_FOR_K (INTVAL (op))
       && INTVAL (op) != 0)
     return 1;
@@ -124,7 +124,7 @@
   if (register_operand (op, mode))
     return 1;
 
-  if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (INTVAL (op)))
+  if (CONST_INT_P (op) && CONST_OK_FOR_M (INTVAL (op)))
     return 1;
 
   return 0;
@@ -138,7 +138,7 @@
   if (register_operand (op, mode))
     return 1;
 
-  if (GET_CODE (op) == CONST_INT)
+  if (CONST_INT_P (op))
     {
       if (CONST_OK_FOR_K (INTVAL (op)) || (mcore_num_zeros (INTVAL (op)) <= 2))
 	return 1;
@@ -156,7 +156,7 @@
   if (register_operand (op, mode))
     return 1;
 
-  if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_O (INTVAL (op)))
+  if (CONST_INT_P (op) && CONST_OK_FOR_O (INTVAL (op)))
     return 1;
 
   return 0;
@@ -170,7 +170,7 @@
   if (register_operand (op, mode))
     return 1;
 
-  if (GET_CODE (op) == CONST_INT && const_ok_for_mcore (INTVAL (op)))
+  if (CONST_INT_P (op) && const_ok_for_mcore (INTVAL (op)))
     return 1;
 
   return 0;
@@ -184,7 +184,7 @@
   if (register_operand (op, mode))
     return 1;
 
-  if (GET_CODE (op) == CONST_INT)
+  if (CONST_INT_P (op))
     return 1;
 
   return 0;
@@ -195,7 +195,7 @@
 (define_predicate "mcore_literal_K_operand"
   (match_code "const_int")
 {
-  if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
+  if (CONST_INT_P (op) && CONST_OK_FOR_K (INTVAL (op)))
     return 1;
 
   return 0;
@@ -209,7 +209,7 @@
   if (register_operand (op, mode))
     return 1;
 
-  if (GET_CODE (op) == CONST_INT)
+  if (CONST_INT_P (op))
     {
       /* The following has been removed because it precludes large constants from being
 	 returned as valid source operands for and add/sub insn.  While large
@@ -242,7 +242,7 @@
   if (register_operand (op, mode))
     return 1;
 
-  if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
+  if (CONST_INT_P (op) && INTVAL (op) == 0)
     return 1;
 
   return 0;
@@ -281,7 +281,7 @@
 	  || GET_MODE (SET_SRC (elt))  != SImode
 	  || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
 	  || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
-	  || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
+	  || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt), 0), 1))
 	  || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
 	return 0;
     }
@@ -321,7 +321,7 @@
 	  || GET_MODE (SET_DEST (elt)) != SImode
 	  || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
 	  || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
-	  || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
+	  || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt), 0), 1))
 	  || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
 	return 0;
     }
diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
index c2cbe3b016c..0569572337d 100644
--- a/gcc/config/microblaze/microblaze.c
+++ b/gcc/config/microblaze/microblaze.c
@@ -314,12 +314,12 @@ simple_memory_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
       if (GET_CODE (plus0) != REG)
         return 0;
 
-      if (GET_CODE (plus0) == REG && GET_CODE (plus1) == CONST_INT
+      if (GET_CODE (plus0) == REG && CONST_INT_P (plus1)
 	  && SMALL_INT (plus1))
 	{
 	  return 1;
 	}
-      else if (GET_CODE (plus1) == REG && GET_CODE (plus0) == CONST_INT)
+      else if (GET_CODE (plus1) == REG && CONST_INT_P (plus0))
 	{
 	  return 1;
 	}
@@ -765,7 +765,7 @@ microblaze_classify_address (struct microblaze_address_info *info, rtx x,
 	    info->type = ADDRESS_REG;
 	    info->regA = xplus0;
 
-	    if (GET_CODE (xplus1) == CONST_INT)
+	    if (CONST_INT_P (xplus1))
 	      {
 		info->offset = xplus1;
 		return true;
@@ -803,7 +803,7 @@ microblaze_classify_address (struct microblaze_address_info *info, rtx x,
 
 		/* for (plus x const_int) just look at x.  */
 		if (GET_CODE (xconst0) == PLUS
-		    && GET_CODE (XEXP (xconst0, 1)) == CONST_INT
+		    && CONST_INT_P (XEXP (xconst0, 1))
 		    && (SMALL_INT (XEXP (xconst0, 1))
 		       || GET_CODE (XEXP (xconst0, 0)) == UNSPEC))
 		  {
@@ -929,7 +929,7 @@ bool
 microblaze_constant_address_p (rtx x)
 {
   return ((GET_CODE (x) == LABEL_REF) || (GET_CODE (x) == SYMBOL_REF)
-	  || GET_CODE (x) == CONST_INT
+	  || CONST_INT_P (x)
 	  || (GET_CODE (x) == CONST
 	  && ! (flag_pic && pic_address_needs_scratch (x))));
 }
@@ -1256,7 +1256,7 @@ bool
 microblaze_expand_block_move (rtx dest, rtx src, rtx length, rtx align_rtx)
 {
 
-  if (GET_CODE (length) == CONST_INT)
+  if (CONST_INT_P (length))
     {
       unsigned HOST_WIDE_INT bytes = UINTVAL (length);
       unsigned int align = UINTVAL (align_rtx);
@@ -1346,7 +1346,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
 	  }
 	else if (!TARGET_SOFT_MUL)
 	  *total = COSTS_N_INSNS (1);
-	else if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+	else if (CONST_INT_P (XEXP (x, 1)))
 	  {
 	    /* Add 1 to make shift slightly more expensive than add.  */
 	    *total = COSTS_N_INSNS (INTVAL (XEXP (x, 1))) + 1;
@@ -1506,7 +1506,7 @@ pic_address_needs_scratch (rtx x)
       p1 = XEXP (XEXP (x, 0), 1);
 
       if ((GET_CODE (p0) == SYMBOL_REF || GET_CODE (p0) == LABEL_REF)
-          && (GET_CODE (p1) == CONST_INT)
+          && (CONST_INT_P (p1))
           && (flag_pic == 2 || microblaze_tls_symbol_p (p0) || !SMALL_INT (p1)))
         return 1;
     }
@@ -2491,19 +2491,19 @@ print_operand (FILE * file, rtx op, int letter)
       print_operand_address (file, op);
     }
 
-  else if (letter == 'x' && GET_CODE (op) == CONST_INT)
+  else if (letter == 'x' && CONST_INT_P (op))
     fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL (op));
 
-  else if (letter == 'X' && GET_CODE (op) == CONST_INT)
+  else if (letter == 'X' && CONST_INT_P (op))
     fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
 
-  else if (letter == 'd' && GET_CODE (op) == CONST_INT)
+  else if (letter == 'd' && CONST_INT_P (op))
     fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL (op)));
 
-  else if (letter == 'z' && GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
+  else if (letter == 'z' && CONST_INT_P (op) && INTVAL (op) == 0)
     fputs (reg_names[GP_REG_FIRST], file);
 
-  else if (letter == 's' && GET_CODE (op) == CONST_INT)
+  else if (letter == 's' && CONST_INT_P (op))
     if (INTVAL (op) < 0)
       fputs ("-1", file);
     else
@@ -3388,7 +3388,7 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
 
   if (!register_operand (op0, SImode)
       && !register_operand (op1, SImode)
-      && (GET_CODE (op1) != CONST_INT || INTVAL (op1) != 0))
+      && (!CONST_INT_P (op1) || INTVAL (op1) != 0))
     {
       rtx temp = force_reg (SImode, op1);
       emit_move_insn (op0, temp);
@@ -3431,7 +3431,7 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
 	  p0 = XEXP (p0, 0);
 	}
 
-      if (GET_CODE (p0) == UNSPEC && GET_CODE (p1) == CONST_INT
+      if (GET_CODE (p0) == UNSPEC && CONST_INT_P (p1)
 	  && flag_pic && TARGET_PIC_DATA_TEXT_REL)
 	{
 	  result = gen_rtx_CONST (Pmode, p0);
@@ -3449,7 +3449,7 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
       p0 = XEXP (XEXP (op1, 0), 0);
       p1 = XEXP (XEXP (op1, 0), 1);
 
-      if ((GET_CODE (p1) == CONST_INT)
+      if ((CONST_INT_P (p1))
 	  && ((GET_CODE (p0) == UNSPEC)
 	      || ((GET_CODE (p0) == SYMBOL_REF || GET_CODE (p0) == LABEL_REF)
 	          && (flag_pic == 2 || microblaze_tls_symbol_p (p0)
@@ -3471,12 +3471,12 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
 int
 microblaze_expand_shift (rtx operands[])
 {
-  gcc_assert ((GET_CODE (operands[2]) == CONST_INT)
+  gcc_assert ((CONST_INT_P (operands[2]))
 	      || (GET_CODE (operands[2]) == REG)
 	      || (GET_CODE (operands[2]) == SUBREG));
 
   /* Shift by one -- generate pattern.  */
-  if ((GET_CODE (operands[2]) == CONST_INT) && (INTVAL (operands[2]) == 1))
+  if ((CONST_INT_P (operands[2])) && (INTVAL (operands[2]) == 1))
     return 0;
 
   /* Have barrel shifter and shift > 1: use it.  */
@@ -3781,7 +3781,7 @@ microblaze_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
         p0 = XEXP (XEXP (x, 0), 0);
         p1 = XEXP (XEXP (x, 0), 1);
 
-        if (GET_CODE(p1) == CONST_INT)
+        if (CONST_INT_P (p1))
           {
             /* Const offset from UNSPEC is not supported.  */
             if ((GET_CODE (p0) == UNSPEC))
diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
index 1509e431859..39e447ba58f 100644
--- a/gcc/config/microblaze/microblaze.md
+++ b/gcc/config/microblaze/microblaze.md
@@ -920,7 +920,7 @@
     if ((reload_in_progress | reload_completed) == 0
         && !register_operand (operands[0], DImode)
         && !register_operand (operands[1], DImode)
-        && (((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
+        && (((!CONST_INT_P (operands[1]) || INTVAL (operands[1]) != 0)
 	       && operands[1] != CONST0_RTX (DImode))))
     {
 
@@ -1017,7 +1017,7 @@
   [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d")
 	(match_operand:SI 1 "immediate_operand" "J,I,Mnis"))]
   "(register_operand (operands[0], SImode) && 
-           (GET_CODE (operands[1]) == CONST_INT && 
+           (CONST_INT_P (operands[1]) && 
                  (INTVAL (operands[1]) <= 32767 && INTVAL (operands[1]) >= -32768)))"  
   "@
    addk\t%0,r0,r0
@@ -1072,7 +1072,7 @@
     if ((reload_in_progress | reload_completed) == 0
         && !register_operand (operands[0], HImode)
         && !register_operand (operands[1], HImode)
-        && ((GET_CODE (operands[1]) != CONST_INT
+        && ((!CONST_INT_P (operands[1])
   	    || INTVAL (operands[1]) != 0)))
     {
         rtx temp = force_reg (HImode, operands[1]);
@@ -1112,7 +1112,7 @@
     if ((reload_in_progress | reload_completed) == 0
         && !register_operand (operands[0], QImode)
         && !register_operand (operands[1], QImode)
-        && ((GET_CODE (operands[1]) != CONST_INT
+        && ((!CONST_INT_P (operands[1])
             || INTVAL (operands[1]) != 0)))
     {
         rtx temp = force_reg (QImode, operands[1]);
@@ -1181,7 +1181,7 @@
     if ((reload_in_progress | reload_completed) == 0
         && !register_operand (operands[0], SFmode)
         && !register_operand (operands[1], SFmode)
-        && ( ((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
+        && ( ((!CONST_INT_P (operands[1]) || INTVAL (operands[1]) != 0)
                  && operands[1] != CONST0_RTX (SFmode))))
     {
         rtx temp = force_reg (SFmode, operands[1]);
@@ -1232,7 +1232,7 @@
     if ((reload_in_progress | reload_completed) == 0
         && !register_operand (operands[0], DFmode)
         && !register_operand (operands[1], DFmode)
-        && (((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
+        && (((!CONST_INT_P (operands[1]) || INTVAL (operands[1]) != 0)
                  && operands[1] != CONST0_RTX (DFmode))))
     {
         rtx temp = force_reg (DFmode, operands[1]);
@@ -1309,7 +1309,7 @@
   ""
   { 
     /* Avoid recursion for trivial cases. */
-    if (!((GET_CODE (operands [2]) == CONST_INT) && (INTVAL (operands[2]) == 1)))
+    if (!((CONST_INT_P (operands [2])) && (INTVAL (operands[2]) == 1)))
       if (microblaze_expand_shift (operands))
         DONE;
   }
@@ -1470,7 +1470,7 @@
   ""
   {
     /* Avoid recursion for trivial cases. */
-    if (!((GET_CODE (operands [2]) == CONST_INT) && (INTVAL (operands[2]) == 1)))
+    if (!((CONST_INT_P (operands [2])) && (INTVAL (operands[2]) == 1)))
       if (microblaze_expand_shift (operands))
         DONE;
   }
@@ -1559,7 +1559,7 @@
   ""
   {
     /* Avoid recursion for trivial cases. */
-    if (!((GET_CODE (operands [2]) == CONST_INT) && (INTVAL (operands[2]) == 1)))
+    if (!((CONST_INT_P (operands [2])) && (INTVAL (operands[2]) == 1)))
       if (microblaze_expand_shift (operands))
         DONE;
   }
@@ -1940,7 +1940,7 @@
     rtx neg_op0;
 
     emit_move_insn (rtmp, retaddr);
-    if (GET_CODE (operands[1]) != CONST_INT)
+    if (!CONST_INT_P (operands[1]))
     {
         neg_op0 = gen_reg_rtx (Pmode);
 	emit_insn (gen_negsi2 (neg_op0, operands[1]));
@@ -2134,7 +2134,7 @@
             gen_rtx_CLOBBER (VOIDmode, target2);
             return "brlid\tr15,%0\;%#";
         }
-    } else if (GET_CODE (target) == CONST_INT)
+    } else if (CONST_INT_P (target))
         return "la\t%@,r0,%0\;brald\tr15,%@\;%#";
     else if (GET_CODE (target) == REG)
         return "brald\tr15,%0\;%#";	
@@ -2249,7 +2249,7 @@
 	    return "bralid\tr15,%1\;%#";
         }
     }
-    else if (GET_CODE (target) == CONST_INT)
+    else if (CONST_INT_P (target))
         return "la\t%@,r0,%1\;brald\tr15,%@\;%#";
     else if (GET_CODE (target) == REG)
         return "brald\tr15,%1\;%#";	
diff --git a/gcc/config/microblaze/predicates.md b/gcc/config/microblaze/predicates.md
index 30f26aeb2f9..7ee237c556b 100644
--- a/gcc/config/microblaze/predicates.md
+++ b/gcc/config/microblaze/predicates.md
@@ -65,7 +65,7 @@
 
                   if ((GET_CODE(p0) == SYMBOL_REF
                        || GET_CODE (p0) == LABEL_REF)
-                      && GET_CODE(p1) == CONST_INT)
+                      && CONST_INT_P (p1))
                     {
                       return arith_plus_operand (p0, GET_MODE(p0));
                     }
@@ -101,7 +101,7 @@
 
 (define_predicate "call_insn_simple_operand"
   (and (match_test "CALL_INSN_OP (op)")
-       (match_test "GET_CODE (op) == REG || GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST_INT")))
+       (match_test "GET_CODE (op) == REG || GET_CODE (op) == SYMBOL_REF || CONST_INT_P (op)")))
 
 ;; Return if OPERAND is valid as a source operand for a move instruction.
 (define_predicate "move_src_operand"
diff --git a/gcc/config/mmix/mmix.c b/gcc/config/mmix/mmix.c
index 380ecde4480..bf443613d84 100644
--- a/gcc/config/mmix/mmix.c
+++ b/gcc/config/mmix/mmix.c
@@ -1063,7 +1063,7 @@ mmix_constant_address_p (rtx x)
 
 	  if ((GET_CODE (x0) == SYMBOL_REF
 	       || GET_CODE (x0) == LABEL_REF)
-	      && (GET_CODE (x1) == CONST_INT
+	      && (CONST_INT_P (x1)
 		  || (GET_CODE (x1) == CONST_DOUBLE
 		      && GET_MODE (x1) == VOIDmode)))
 	    addend = mmix_intval (x1);
@@ -1395,7 +1395,7 @@ mmix_assemble_integer (rtx x, unsigned int size, int aligned_p)
 	   keep as much compatibility as possible with mmixal syntax for
 	   normal cases (i.e. without GNU extensions and C only).  */
       case 1:
-	if (GET_CODE (x) != CONST_INT)
+	if (!CONST_INT_P (x))
 	  {
 	    /* There is no "unaligned byte" op or generic function to
 	       which we can punt, so we have to handle this here.  As
@@ -1412,7 +1412,7 @@ mmix_assemble_integer (rtx x, unsigned int size, int aligned_p)
 	return true;
 
       case 2:
-	if (GET_CODE (x) != CONST_INT)
+	if (!CONST_INT_P (x))
 	  {
 	    aligned_p = 0;
 	    break;
@@ -1423,7 +1423,7 @@ mmix_assemble_integer (rtx x, unsigned int size, int aligned_p)
 	return true;
 
       case 4:
-	if (GET_CODE (x) != CONST_INT)
+	if (!CONST_INT_P (x))
 	  {
 	    aligned_p = 0;
 	    break;
@@ -1599,7 +1599,7 @@ mmix_print_operand (FILE *stream, rtx x, int code)
       return;
 
     case 'B':
-      if (GET_CODE (x) != CONST_INT)
+      if (!CONST_INT_P (x))
 	fatal_insn ("MMIX Internal: Expected a CONST_INT, not this", x);
       fprintf (stream, "%d", (int) (INTVAL (x) & 0xff));
       return;
@@ -1617,7 +1617,7 @@ mmix_print_operand (FILE *stream, rtx x, int code)
     case 'L':
       /* Lowpart.  Must be CONST_INT or general register, and not the last
 	 one, as that one cannot be part of a consecutive register pair.  */
-      if (GET_CODE (x) == CONST_INT)
+      if (CONST_INT_P (x))
 	{
 	  fprintf (stream, "#%lx",
 		   (unsigned long) (INTVAL (x)
@@ -1677,7 +1677,7 @@ mmix_print_operand (FILE *stream, rtx x, int code)
 
     case 'm':
       /* Output the number minus 1.  */
-      if (GET_CODE (x) != CONST_INT)
+      if (!CONST_INT_P (x))
 	{
 	  fatal_insn ("MMIX Internal: Bad value for 'm', not a CONST_INT",
 		      x);
@@ -1704,7 +1704,7 @@ mmix_print_operand (FILE *stream, rtx x, int code)
 
     case 'I':
       /* Output the constant.  Note that we use this for floats as well.  */
-      if (GET_CODE (x) != CONST_INT
+      if (!CONST_INT_P (x)
 	  && (GET_CODE (x) != CONST_DOUBLE
 	      || (GET_MODE (x) != VOIDmode && GET_MODE (x) != DFmode
 		  && GET_MODE (x) != SFmode)))
@@ -1729,7 +1729,7 @@ mmix_print_operand (FILE *stream, rtx x, int code)
       return;
 
     case 'W':
-      if (GET_CODE (x) != CONST_INT)
+      if (!CONST_INT_P (x))
 	fatal_insn ("MMIX Internal: Expected a CONST_INT, not this", x);
       fprintf (stream, "#%x", (int) (INTVAL (x) & 0xffff));
       return;
@@ -2743,7 +2743,7 @@ mmix_output_condition (FILE *stream, const_rtx x, int reversed)
 int64_t
 mmix_intval (const_rtx x)
 {
-  if (GET_CODE (x) == CONST_INT)
+  if (CONST_INT_P (x))
     return INTVAL (x);
 
   /* We make a little song and dance because converting to long long in
diff --git a/gcc/config/mmix/mmix.md b/gcc/config/mmix/mmix.md
index 8a0c311f893..bf28b63a16b 100644
--- a/gcc/config/mmix/mmix.md
+++ b/gcc/config/mmix/mmix.md
@@ -1192,7 +1192,7 @@ DIVU %1,%1,%2\;GET %0,:rR\;NEGU %2,0,%0\;CSNN %0,$255,%2")
 	(plus:DI (mult:DI (match_operand:DI 1 "register_operand" "r")
 			  (match_operand:DI 2 "const_int_operand" "n"))
 		 (match_operand:DI 3 "mmix_reg_or_8bit_operand" "rI")))]
-  "GET_CODE (operands[2]) == CONST_INT
+  "CONST_INT_P (operands[2])
    && (INTVAL (operands[2]) == 2
        || INTVAL (operands[2]) == 4
        || INTVAL (operands[2]) == 8
diff --git a/gcc/config/mmix/predicates.md b/gcc/config/mmix/predicates.md
index 1d446c54dc7..c572b7b07b1 100644
--- a/gcc/config/mmix/predicates.md
+++ b/gcc/config/mmix/predicates.md
@@ -112,7 +112,7 @@
       op = XEXP (op, 0);
       if ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
 	   || GET_CODE (XEXP (op, 0)) == LABEL_REF)
-	  && (GET_CODE (XEXP (op, 1)) == CONST_INT
+	  && (CONST_INT_P (XEXP (op, 1))
 	      || (GET_CODE (XEXP (op, 1)) == CONST_DOUBLE
 		  && GET_MODE (XEXP (op, 1)) == VOIDmode)))
 	return 1;
diff --git a/gcc/config/moxie/moxie.c b/gcc/config/moxie/moxie.c
index 0284f3c40a4..7f1bb5aac95 100644
--- a/gcc/config/moxie/moxie.c
+++ b/gcc/config/moxie/moxie.c
@@ -562,7 +562,7 @@ moxie_offset_address_p (rtx x)
   if (GET_CODE (x) == PLUS)
     {
       x = XEXP (x, 1);
-      if (GET_CODE (x) == CONST_INT)
+      if (CONST_INT_P (x))
 	{
 	  unsigned int v = INTVAL (x) & 0xFFFF8000;
 	  return (v == 0xFFFF8000 || v == 0x00000000);
diff --git a/gcc/config/moxie/predicates.md b/gcc/config/moxie/predicates.md
index 7c0c5b5b489..b7deba669ca 100644
--- a/gcc/config/moxie/predicates.md
+++ b/gcc/config/moxie/predicates.md
@@ -34,7 +34,7 @@
   if (MEM_P (op)
       && GET_CODE (XEXP (op, 0)) == PLUS
       && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
-      && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
+      && CONST_INT_P (XEXP (XEXP (op, 0), 1))
       && IN_RANGE (INTVAL (XEXP (XEXP (op, 0), 1)), -32768, 32767))
     return 1;
 
diff --git a/gcc/config/msp430/msp430.c b/gcc/config/msp430/msp430.c
index c7b774e71a6..c7f04a0bfa5 100644
--- a/gcc/config/msp430/msp430.c
+++ b/gcc/config/msp430/msp430.c
@@ -2617,7 +2617,7 @@ msp430_expand_delay_cycles (rtx arg)
   /* extra cycles for MSP430X instructions */
 #define CYCX(M,X) (msp430x ? (X) : (M))
 
-  if (GET_CODE (arg) != CONST_INT)
+  if (!CONST_INT_P (arg))
     {
       error ("__delay_cycles() only takes constant arguments");
       return NULL_RTX;
@@ -3609,7 +3609,7 @@ msp430_print_operand (FILE * file, rtx op, int letter)
       fprintf (file, "#%ld", INTVAL (op) - 4);
       return;
     case 'I':
-      if (GET_CODE (op) == CONST_INT)
+      if (CONST_INT_P (op))
 	{
 	  /* Inverse of constants */
 	  int i = INTVAL (op);
@@ -3768,7 +3768,7 @@ msp430_print_operand (FILE * file, rtx op, int letter)
       return;
 
     case 'J':
-      gcc_assert (GET_CODE (op) == CONST_INT);
+      gcc_assert (CONST_INT_P (op));
     case 0:
       break;
     default:
diff --git a/gcc/config/msp430/msp430.md b/gcc/config/msp430/msp430.md
index f6d688950cb..b516ec15462 100644
--- a/gcc/config/msp430/msp430.md
+++ b/gcc/config/msp430/msp430.md
@@ -435,7 +435,7 @@
        || reg_overlap_mentioned_p (operands[3], operands[8]))
       FAIL;
 
-   if (GET_CODE (operands[5]) == CONST_INT)
+   if (CONST_INT_P (operands[5]))
      operands[9] = GEN_INT (INTVAL (operands[5]) & 0xffff);
    else
      operands[9] = gen_rtx_ZERO_EXTEND (SImode, operands[5]);
diff --git a/gcc/config/nds32/nds32-cost.c b/gcc/config/nds32/nds32-cost.c
index 09b22cad494..010a5ce6402 100644
--- a/gcc/config/nds32/nds32-cost.c
+++ b/gcc/config/nds32/nds32-cost.c
@@ -171,7 +171,7 @@ nds32_rtx_costs_speed_prefer (rtx x ATTRIBUTE_UNUSED,
 	/* ALU_SHIFT */
 	*total = COSTS_N_INSNS (2);
 
-      else if ((GET_CODE (op1) == CONST_INT
+      else if ((CONST_INT_P (op1)
 		&& satisfies_constraint_Is15 (op1))
 		|| REG_P (op1))
 	/* ADD instructions */
@@ -191,7 +191,7 @@ nds32_rtx_costs_speed_prefer (rtx x ATTRIBUTE_UNUSED,
 	       || GET_CODE (op1) == MULT || GET_CODE (op1) == LSHIFTRT)
 	/* ALU_SHIFT */
 	*total = COSTS_N_INSNS (2);
-      else if ((GET_CODE (op0) == CONST_INT
+      else if ((CONST_INT_P (op0)
 		&& satisfies_constraint_Is15 (op0))
 		|| REG_P (op0))
 	/* SUB instructions */
@@ -227,7 +227,7 @@ nds32_rtx_costs_speed_prefer (rtx x ATTRIBUTE_UNUSED,
 	*total = cost;
       else if (GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFTRT)
 	*total = COSTS_N_INSNS (2);
-      else if ((GET_CODE (op1) == CONST_INT
+      else if ((CONST_INT_P (op1)
 	       && satisfies_constraint_Iu15 (op1))
 	       || REG_P (op1))
 	/* AND, OR, XOR instructions */
@@ -250,7 +250,7 @@ nds32_rtx_costs_speed_prefer (rtx x ATTRIBUTE_UNUSED,
 	*total = cost;
       else if (outer_code == PLUS || outer_code == MINUS)
 	*total = COSTS_N_INSNS (2);
-      else if ((GET_CODE (XEXP (x, 1)) == CONST_INT
+      else if ((CONST_INT_P (XEXP (x, 1))
 	       && satisfies_constraint_Iu05 (XEXP (x, 1)))
 	       || REG_P (XEXP (x, 1)))
 	/* MUL instructions */
@@ -271,7 +271,7 @@ nds32_rtx_costs_speed_prefer (rtx x ATTRIBUTE_UNUSED,
 	       || outer_code == AND || outer_code == IOR
 	       || outer_code == XOR)
 	*total = COSTS_N_INSNS (2);
-      else if ((GET_CODE (XEXP (x, 1)) == CONST_INT
+      else if ((CONST_INT_P (XEXP (x, 1))
 	       && satisfies_constraint_Iu05 (XEXP (x, 1)))
 	       || REG_P (XEXP (x, 1)))
 	/* SRL instructions */
@@ -287,7 +287,7 @@ nds32_rtx_costs_speed_prefer (rtx x ATTRIBUTE_UNUSED,
       else if (outer_code == AND || outer_code == IOR
 	       || outer_code == XOR)
 	*total = COSTS_N_INSNS (2);
-      else if ((GET_CODE (XEXP (x, 1)) == CONST_INT
+      else if ((CONST_INT_P (XEXP (x, 1))
 	       && satisfies_constraint_Iu05 (XEXP (x, 1)))
 	       || REG_P (XEXP (x, 1)))
 	/* SLL instructions */
@@ -301,7 +301,7 @@ nds32_rtx_costs_speed_prefer (rtx x ATTRIBUTE_UNUSED,
     case ROTATERT:
       if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (DImode))
 	*total = cost;
-      else if ((GET_CODE (XEXP (x, 1)) == CONST_INT
+      else if ((CONST_INT_P (XEXP (x, 1))
 	       && satisfies_constraint_Iu05 (XEXP (x, 1)))
 	       || REG_P (XEXP (x, 1)))
 	/* ROTR, SLL instructions */
@@ -315,7 +315,7 @@ nds32_rtx_costs_speed_prefer (rtx x ATTRIBUTE_UNUSED,
     case LTU:
       if (outer_code == SET)
 	{
-	  if ((GET_CODE (XEXP (x, 1)) == CONST_INT
+	  if ((CONST_INT_P (XEXP (x, 1))
 	      && satisfies_constraint_Iu15 (XEXP (x, 1)))
 	      || REG_P (XEXP (x, 1)))
 	    /* SLT, SLTI instructions */
diff --git a/gcc/config/nds32/nds32-intrinsic.c b/gcc/config/nds32/nds32-intrinsic.c
index c78dc935bf3..5c5a2babc0e 100644
--- a/gcc/config/nds32/nds32-intrinsic.c
+++ b/gcc/config/nds32/nds32-intrinsic.c
@@ -121,7 +121,7 @@ static int
 nds32_check_constant_argument (enum insn_code icode, int opnum, rtx opval,
 			       const char *name)
 {
-  if (GET_CODE (opval) != CONST_INT)
+  if (!CONST_INT_P (opval))
     {
       error ("invalid argument to built-in function %s", name);
       return false;
diff --git a/gcc/config/nds32/nds32-md-auxiliary.c b/gcc/config/nds32/nds32-md-auxiliary.c
index eadd8417878..3e6371730d0 100644
--- a/gcc/config/nds32/nds32-md-auxiliary.c
+++ b/gcc/config/nds32/nds32-md-auxiliary.c
@@ -391,7 +391,7 @@ nds32_expand_cbranch (rtx *operands)
   /* If operands[2] is (const_int 0),
      we can use beqz,bnez,bgtz,bgez,bltz,or blez instructions.
      So we have gcc generate original template rtx.  */
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     if (INTVAL (operands[2]) == 0)
       if ((code != GTU)
 	  && (code != GEU)
@@ -406,7 +406,7 @@ nds32_expand_cbranch (rtx *operands)
     {
     case GT:
     case GTU:
-      if (GET_CODE (operands[2]) == CONST_INT)
+      if (CONST_INT_P (operands[2]))
 	{
 	  /* GT  reg_A, const_int  =>  !(LT  reg_A, const_int + 1) */
 	  if (optimize_size || optimize == 0)
@@ -560,7 +560,7 @@ nds32_expand_cbranch (rtx *operands)
 
     case LE:
     case LEU:
-      if (GET_CODE (operands[2]) == CONST_INT)
+      if (CONST_INT_P (operands[2]))
 	{
 	  /* LE  reg_A, const_int  =>  LT  reg_A, const_int + 1 */
 	  if (optimize_size || optimize == 0)
@@ -651,7 +651,7 @@ nds32_expand_cbranch (rtx *operands)
 
       /* Put operands[2] into register if operands[2] is a large
 	 const_int or ISAv2.  */
-      if (GET_CODE (operands[2]) == CONST_INT
+      if (CONST_INT_P (operands[2])
 	  && (!satisfies_constraint_Is11 (operands[2])
 	      || TARGET_ISA_V2))
 	operands[2] = force_reg (SImode, operands[2]);
@@ -675,7 +675,7 @@ nds32_expand_cstore (rtx *operands)
     {
     case EQ:
     case NE:
-      if (GET_CODE (operands[3]) == CONST_INT)
+      if (CONST_INT_P (operands[3]))
 	{
 	  /* reg_R = (reg_A == const_int_B)
 	     --> xori reg_C, reg_A, const_int_B
@@ -743,7 +743,7 @@ nds32_expand_cstore (rtx *operands)
 
     case GE:
     case GEU:
-      if (GET_CODE (operands[3]) == CONST_INT)
+      if (CONST_INT_P (operands[3]))
 	{
 	  /* reg_R = (reg_A >= const_int_B)
 	     --> movi reg_C, const_int_B - 1
@@ -809,7 +809,7 @@ nds32_expand_cstore (rtx *operands)
 
     case LE:
     case LEU:
-      if (GET_CODE (operands[3]) == CONST_INT)
+      if (CONST_INT_P (operands[3]))
 	{
 	  /* reg_R = (reg_A <= const_int_B)
 	     --> movi reg_C, const_int_B + 1
@@ -1518,7 +1518,7 @@ nds32_mem_format (rtx op)
 
   if ((GET_CODE (op) == PLUS)
       && (GET_CODE (XEXP (op, 0)) == REG)
-      && (GET_CODE (XEXP (op, 1)) == CONST_INT))
+      && (CONST_INT_P (XEXP (op, 1))))
     {
       val = INTVAL (XEXP (op, 1));
 
@@ -3535,7 +3535,7 @@ nds32_legitimize_pic_address (rtx x)
 	   || (GET_CODE (op0) == SYMBOL_REF
 	       && (CONSTANT_POOL_ADDRESS_P (op0)
 		   || SYMBOL_REF_LOCAL_P (op0))))
-	  && GET_CODE (op1) == CONST_INT)
+	  && CONST_INT_P (op1))
 	{
 	  pat = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0), UNSPEC_GOTOFF);
 	  pat = gen_rtx_PLUS (Pmode, pat, op1);
@@ -3544,7 +3544,7 @@ nds32_legitimize_pic_address (rtx x)
 	  x = gen_rtx_PLUS (Pmode, reg, pic_offset_table_rtx);
 	}
       else if (GET_CODE (op0) == SYMBOL_REF
-	       && GET_CODE (op1) == CONST_INT)
+	       && CONST_INT_P (op1))
 	{
 	  /* This is a constant offset from a @GOT symbol reference.  */
 	  addr = gen_rtx_UNSPEC (SImode, gen_rtvec (1, op0), UNSPEC_GOT);
diff --git a/gcc/config/nds32/nds32-memory-manipulation.c b/gcc/config/nds32/nds32-memory-manipulation.c
index b3f2cd69899..9f320118c1c 100644
--- a/gcc/config/nds32/nds32-memory-manipulation.c
+++ b/gcc/config/nds32/nds32-memory-manipulation.c
@@ -435,8 +435,8 @@ nds32_expand_cpymemsi_unroll (rtx dstmem, rtx srcmem,
      5. The srcmem cannot be volatile memory access.
      6. Known shared alignment not align to 4 byte in v3m since lmw/smw *NOT*
 	support unalign access with v3m configure.  */
-  if (GET_CODE (total_bytes) != CONST_INT
-      || GET_CODE (alignment) != CONST_INT
+  if (!CONST_INT_P (total_bytes)
+      || !CONST_INT_P (alignment)
       || INTVAL (total_bytes) > maximum_bytes
       || MEM_VOLATILE_P (dstmem)
       || MEM_VOLATILE_P (srcmem)
diff --git a/gcc/config/nds32/nds32-multiple.md b/gcc/config/nds32/nds32-multiple.md
index 98d9508c06b..96810fabecd 100644
--- a/gcc/config/nds32/nds32-multiple.md
+++ b/gcc/config/nds32/nds32-multiple.md
@@ -56,7 +56,7 @@
        5. operands[1] must be memory for sure.
        6. operands[1] is not volatile memory access.
        7. Do not cross $r15 register because it is not allocatable.  */
-  if (GET_CODE (operands[2]) != CONST_INT
+  if (!CONST_INT_P (operands[2])
       || INTVAL (operands[2]) > maximum
       || INTVAL (operands[2]) < 2
       || GET_CODE (operands[0]) != REG
@@ -1905,7 +1905,7 @@
        5. operands[1] must be register for sure.
        6. operands[0] is not volatile memory access.
        7. Do not cross $r15 register because it is not allocatable.  */
-  if (GET_CODE (operands[2]) != CONST_INT
+  if (!CONST_INT_P (operands[2])
       || INTVAL (operands[2]) > maximum
       || INTVAL (operands[2]) < 2
       || GET_CODE (operands[0]) != MEM
diff --git a/gcc/config/nds32/nds32-pipelines-auxiliary.c b/gcc/config/nds32/nds32-pipelines-auxiliary.c
index 07ba0378783..09ad3d59af3 100644
--- a/gcc/config/nds32/nds32-pipelines-auxiliary.c
+++ b/gcc/config/nds32/nds32-pipelines-auxiliary.c
@@ -146,7 +146,7 @@ determine_access_direction (rtx_insn *insn)
   gcc_assert (GET_CODE (plus_rtx) == PLUS);
 
   offset_rtx = XEXP (plus_rtx, 1);
-  if (GET_CODE (offset_rtx) == CONST_INT)
+  if (CONST_INT_P (offset_rtx))
     {
       if (INTVAL (offset_rtx) < 0)
 	return MEM_ACCESS_DIR_NEG;
@@ -1378,7 +1378,7 @@ nds32_e8_ex_to_ii_p (rtx_insn *producer, rtx_insn *consumer)
 	  rtx src = SET_SRC (PATTERN (producer));
 
 	  if ((REG_P (dest) || GET_CODE (dest) == SUBREG)
-	      && (GET_CODE (src) == CONST_INT || GET_CODE (src) == HIGH))
+	      && (CONST_INT_P (src) || GET_CODE (src) == HIGH))
 	    return false;
 	}
 
diff --git a/gcc/config/nds32/nds32-predicates.c b/gcc/config/nds32/nds32-predicates.c
index eef34904fe1..8d02ce5a77b 100644
--- a/gcc/config/nds32/nds32-predicates.c
+++ b/gcc/config/nds32/nds32-predicates.c
@@ -171,7 +171,7 @@ nds32_valid_multiple_load_store_p (rtx op, bool load_p, bool bim_p)
 	{
 	  offset = count * UNITS_PER_WORD;
 	  elt = XEXP (SET_SRC (update_base), 1);
-	  if (GET_CODE (elt) != CONST_INT
+	  if (!CONST_INT_P (elt)
 	      || (INTVAL (elt) != offset))
 	    return false;
 	}
@@ -471,7 +471,7 @@ nds32_float_mem_operand_p (rtx op)
 	return false;
 
       /* Restrict const range: (imm12s << 2) */
-      if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
+      if (CONST_INT_P (XEXP (addr, 1)))
 	{
 	  if ((mode == SImode || mode == SFmode)
 	      && NDS32_SINGLE_WORD_ALIGN_P (INTVAL (XEXP (addr, 1)))
diff --git a/gcc/config/nds32/nds32-utils.c b/gcc/config/nds32/nds32-utils.c
index 3515e610456..96ee791de54 100644
--- a/gcc/config/nds32/nds32-utils.c
+++ b/gcc/config/nds32/nds32-utils.c
@@ -184,7 +184,7 @@ immed_offset_p (rtx mem_rtx)
 
   /* (mem (plus (reg) (const_int))) */
   if (GET_CODE (addr_rtx) == PLUS
-      && GET_CODE (XEXP (addr_rtx, 1)) == CONST_INT)
+      && CONST_INT_P (XEXP (addr_rtx, 1)))
     return true;
 
   return false;
diff --git a/gcc/config/nds32/nds32.c b/gcc/config/nds32/nds32.c
index eba98126705..c3a9d27f137 100644
--- a/gcc/config/nds32/nds32.c
+++ b/gcc/config/nds32/nds32.c
@@ -3396,7 +3396,7 @@ nds32_print_operand (FILE *stream, rtx x, int code)
     case 'e':
       gcc_assert (MEM_P (x)
 		  && GET_CODE (XEXP (x, 0)) == PLUS
-		  && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT);
+		  && CONST_INT_P (XEXP (XEXP (x, 0), 1)));
       fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (XEXP (XEXP (x, 0), 1)));
 
       /* No need to handle following process, so return immediately.  */
diff --git a/gcc/config/nios2/nios2.c b/gcc/config/nios2/nios2.c
index 250c6ac4b08..6893ebb1528 100644
--- a/gcc/config/nios2/nios2.c
+++ b/gcc/config/nios2/nios2.c
@@ -3095,7 +3095,7 @@ r0rel_constant_p (rtx op)
   else if (GET_CODE (op) == CONST
            && GET_CODE (XEXP (op, 0)) == PLUS)
     return r0rel_constant_p (XEXP (XEXP (op, 0), 0));
-  else if (GET_CODE (op) == CONST_INT
+  else if (CONST_INT_P (op)
 	   && SMALL_INT (INTVAL (op)))
     return true;
 
diff --git a/gcc/config/nvptx/nvptx.c b/gcc/config/nvptx/nvptx.c
index c53a1ae9f26..3107ea58818 100644
--- a/gcc/config/nvptx/nvptx.c
+++ b/gcc/config/nvptx/nvptx.c
@@ -5271,7 +5271,7 @@ nvptx_expand_shuffle (tree exp, rtx target, machine_mode mode, int ignore)
   rtx op = expand_expr (CALL_EXPR_ARG  (exp, 2),
 			NULL_RTX, SImode, EXPAND_NORMAL);
   
-  if (!REG_P (idx) && GET_CODE (idx) != CONST_INT)
+  if (!REG_P (idx) && !CONST_INT_P (idx))
     idx = copy_to_mode_reg (SImode, idx);
 
   rtx pat = nvptx_gen_shuffle (target, src, idx,
diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index f54ca6e4abf..565221e7fb2 100644
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -899,7 +899,7 @@ legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
       orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
 				     base == reg ? 0 : reg);
 
-      if (GET_CODE (orig) == CONST_INT)
+      if (CONST_INT_P (orig))
 	{
 	  if (INT_14_BITS (orig))
 	    return plus_constant (Pmode, base, INTVAL (orig));
@@ -1009,7 +1009,7 @@ mem_shadd_or_shadd_rtx_p (rtx x)
 {
   return ((GET_CODE (x) == ASHIFT
 	   || GET_CODE (x) == MULT)
-	  && GET_CODE (XEXP (x, 1)) == CONST_INT
+	  && CONST_INT_P (XEXP (x, 1))
 	  && ((GET_CODE (x) == ASHIFT
 	       && pa_shadd_constant_p (INTVAL (XEXP (x, 1))))
 	      || (GET_CODE (x) == MULT
@@ -1111,7 +1111,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
   /* Note we must reject symbols which represent function addresses
      since the assembler/linker can't handle arithmetic on plabels.  */
   if (GET_CODE (x) == PLUS
-      && GET_CODE (XEXP (x, 1)) == CONST_INT
+      && CONST_INT_P (XEXP (x, 1))
       && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
 	   && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
 	  || GET_CODE (XEXP (x, 0)) == REG))
@@ -1251,7 +1251,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
 
       /* If the index adds a large constant, try to scale the
 	 constant so that it can be loaded with only one insn.  */
-      if (GET_CODE (XEXP (idx, 1)) == CONST_INT
+      if (CONST_INT_P (XEXP (idx, 1))
 	  && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
 			    / INTVAL (XEXP (XEXP (idx, 0), 1)))
 	  && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
@@ -1276,7 +1276,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
 	}
 
       /* If B + C is still a valid base register, then add them.  */
-      if (GET_CODE (XEXP (idx, 1)) == CONST_INT
+      if (CONST_INT_P (XEXP (idx, 1))
 	  && INTVAL (XEXP (idx, 1)) <= 4096
 	  && INTVAL (XEXP (idx, 1)) >= -4096)
 	{
@@ -1285,7 +1285,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
 	  reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
 
 	  reg2 = XEXP (XEXP (idx, 0), 0);
-	  if (GET_CODE (reg2) != CONST_INT)
+	  if (!CONST_INT_P (reg2))
 	    reg2 = force_reg (Pmode, force_operand (reg2, 0));
 
 	  return force_reg (Pmode,
@@ -1357,7 +1357,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
 	     and added to (reg).  This allows more scaled indexed addresses.  */
 	  if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
 	      && mem_shadd_or_shadd_rtx_p (XEXP (x, 0))
-	      && GET_CODE (XEXP (y, 1)) == CONST_INT
+	      && CONST_INT_P (XEXP (y, 1))
 	      && INTVAL (XEXP (y, 1)) >= -4096
 	      && INTVAL (XEXP (y, 1)) <= 4095)
 	    {
@@ -1389,7 +1389,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
 	  else if ((mode == DFmode || mode == SFmode)
 		   && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
 		   && mem_shadd_or_shadd_rtx_p (XEXP (x, 0))
-		   && GET_CODE (XEXP (y, 1)) == CONST_INT
+		   && CONST_INT_P (XEXP (y, 1))
 		   && INTVAL (XEXP (y, 1)) % (1 << INTVAL (XEXP (XEXP (x, 0), 1))) == 0)
 	    {
 	      int shift_val = INTVAL (XEXP (XEXP (x, 0), 1));
@@ -1414,7 +1414,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
 						         GEN_INT (shift_val)),
 					 force_reg (Pmode, XEXP (y, 0))));
 	    }
-	  else if (GET_CODE (XEXP (y, 1)) == CONST_INT
+	  else if (CONST_INT_P (XEXP (y, 1))
 		   && INTVAL (XEXP (y, 1)) >= -4096
 		   && INTVAL (XEXP (y, 1)) <= 4095)
 	    {
@@ -1855,7 +1855,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
 	   && GET_CODE (operand0) == REG
 	   && REGNO (operand0) < FIRST_PSEUDO_REGISTER
 	   && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
-	   && (GET_CODE (operand1) == MEM || GET_CODE (operand1) == CONST_INT))
+	   && (GET_CODE (operand1) == MEM || CONST_INT_P (operand1)))
     {
       /* D might not fit in 14 bits either; for such cases load D into
 	 scratch reg.  */
@@ -1908,7 +1908,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
 	operand1 = legitimize_tls_address (operand1);
 
       if (register_operand (operand1, mode)
-	  || (GET_CODE (operand1) == CONST_INT
+	  || (CONST_INT_P (operand1)
 	      && pa_cint_ok_for_move (UINTVAL (operand1)))
 	  || (operand1 == CONST0_RTX (mode))
 	  || (GET_CODE (operand1) == HIGH
@@ -2035,7 +2035,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
 		{
 		  /* Save away the constant part of the expression.  */
 		  const_part = XEXP (XEXP (operand1, 0), 1);
-		  gcc_assert (GET_CODE (const_part) == CONST_INT);
+		  gcc_assert (CONST_INT_P (const_part));
 
 		  /* Force the function label into memory.  */
 		  temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
@@ -2095,7 +2095,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
 		 needed to load the value is shorter.  */
 	      if (GET_CODE (operand1) == CONST
 		       && GET_CODE (XEXP (operand1, 0)) == PLUS
-		       && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
+		       && CONST_INT_P (XEXP (XEXP (operand1, 0), 1))
 		       && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1)))
 		{
 		  rtx x, m = force_const_mem (mode, operand1);
@@ -2175,7 +2175,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
 	    }
 	  operands[1] = tmp;
 	}
-      else if (GET_CODE (operand1) != CONST_INT
+      else if (!CONST_INT_P (operand1)
 	       || !pa_cint_ok_for_move (UINTVAL (operand1)))
 	{
 	  rtx temp;
@@ -2185,11 +2185,11 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
 	  HOST_WIDE_INT insv = 0;
 	  int insert = 0;
 
-	  if (GET_CODE (operand1) == CONST_INT)
+	  if (CONST_INT_P (operand1))
 	    value = INTVAL (operand1);
 
 	  if (TARGET_64BIT
-	      && GET_CODE (operand1) == CONST_INT
+	      && CONST_INT_P (operand1)
 	      && HOST_BITS_PER_WIDE_INT > 32
 	      && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
 	    {
@@ -2221,7 +2221,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
 	  /* We don't directly split DImode constants on 32-bit targets
 	     because PLUS uses an 11-bit immediate and the insn sequence
 	     generated is not as efficient as the one using HIGH/LO_SUM.  */
-	  if (GET_CODE (operand1) == CONST_INT
+	  if (CONST_INT_P (operand1)
 	      && GET_MODE_BITSIZE (mode) <= BITS_PER_WORD
 	      && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
 	      && !insert)
@@ -2397,7 +2397,7 @@ pa_singlemove_string (rtx *operands)
       operands[1] = GEN_INT (i);
       /* Fall through to CONST_INT case.  */
     }
-  if (GET_CODE (operands[1]) == CONST_INT)
+  if (CONST_INT_P (operands[1]))
     {
       intval = INTVAL (operands[1]);
 
@@ -3160,7 +3160,7 @@ compute_clrmem_length (rtx_insn *insn)
 const char *
 pa_output_and (rtx *operands)
 {
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
+  if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) != 0)
     {
       unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
       int ls0, ls1, ms0, p, len;
@@ -3210,7 +3210,7 @@ pa_output_and (rtx *operands)
 const char *
 pa_output_64bit_and (rtx *operands)
 {
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
+  if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) != 0)
     {
       unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
       int ls0, ls1, ms0, p, len;
@@ -5320,36 +5320,36 @@ pa_print_operand (FILE *file, rtx x, int code)
 	}
       return;
     case 'k':
-      gcc_assert (GET_CODE (x) == CONST_INT);
+      gcc_assert (CONST_INT_P (x));
       fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
       return;
     case 'Q':
-      gcc_assert (GET_CODE (x) == CONST_INT);
+      gcc_assert (CONST_INT_P (x));
       fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
       return;
     case 'L':
-      gcc_assert (GET_CODE (x) == CONST_INT);
+      gcc_assert (CONST_INT_P (x));
       fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
       return;
     case 'o':
-      gcc_assert (GET_CODE (x) == CONST_INT
+      gcc_assert (CONST_INT_P (x)
 		  && (INTVAL (x) == 1 || INTVAL (x) == 2 || INTVAL (x) == 3));
       fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
       return;
     case 'O':
-      gcc_assert (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0);
+      gcc_assert (CONST_INT_P (x) && exact_log2 (INTVAL (x)) >= 0);
       fprintf (file, "%d", exact_log2 (INTVAL (x)));
       return;
     case 'p':
-      gcc_assert (GET_CODE (x) == CONST_INT);
+      gcc_assert (CONST_INT_P (x));
       fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
       return;
     case 'P':
-      gcc_assert (GET_CODE (x) == CONST_INT);
+      gcc_assert (CONST_INT_P (x));
       fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
       return;
     case 'I':
-      if (GET_CODE (x) == CONST_INT)
+      if (CONST_INT_P (x))
 	fputs ("i", file);
       return;
     case 'M':
@@ -5847,7 +5847,7 @@ static int div_milli[16][2];
 int
 pa_emit_hpdiv_const (rtx *operands, int unsignedp)
 {
-  if (GET_CODE (operands[2]) == CONST_INT
+  if (CONST_INT_P (operands[2])
       && INTVAL (operands[2]) > 0
       && INTVAL (operands[2]) < 16
       && pa_magic_milli[INTVAL (operands[2])])
@@ -5881,7 +5881,7 @@ pa_output_div_insn (rtx *operands, int unsignedp, rtx_insn *insn)
 
   /* If the divisor is a constant, try to use one of the special
      opcodes .*/
-  if (GET_CODE (operands[0]) == CONST_INT)
+  if (CONST_INT_P (operands[0]))
     {
       static char buf[100];
       divisor = INTVAL (operands[0]);
@@ -6055,7 +6055,7 @@ pa_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
      a few patterns that accept constant double operands.  */
   if (flag_pic
       && FP_REG_CLASS_P (rclass)
-      && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
+      && (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE))
     {
       switch (mode)
 	{
@@ -8358,7 +8358,7 @@ pa_is_function_label_plus_const (rtx op)
 
   return (GET_CODE (op) == PLUS
 	  && function_label_operand (XEXP (op, 0), VOIDmode)
-	  && GET_CODE (XEXP (op, 1)) == CONST_INT);
+	  && CONST_INT_P (XEXP (op, 1)));
 }
 
 /* Output assembly code for a thunk to FUNCTION.  */
@@ -8952,7 +8952,7 @@ pa_output_parallel_movb (rtx *operands, rtx_insn *insn)
 	{
 	  /* Nothing in the delay slot, fake it by putting the combined
 	     insn (the copy or add) in the delay slot of a bl.  */
-	  if (GET_CODE (operands[1]) == CONST_INT)
+	  if (CONST_INT_P (operands[1]))
 	    return "b %2\n\tldi %1,%0";
 	  else
 	    return "b %2\n\tcopy %1,%0";
@@ -8960,14 +8960,14 @@ pa_output_parallel_movb (rtx *operands, rtx_insn *insn)
       else
 	{
 	  /* Something in the delay slot, but we've got a long branch.  */
-	  if (GET_CODE (operands[1]) == CONST_INT)
+	  if (CONST_INT_P (operands[1]))
 	    return "ldi %1,%0\n\tb %2";
 	  else
 	    return "copy %1,%0\n\tb %2";
 	}
     }
 
-  if (GET_CODE (operands[1]) == CONST_INT)
+  if (CONST_INT_P (operands[1]))
     output_asm_insn ("ldi %1,%0", operands);
   else
     output_asm_insn ("copy %1,%0", operands);
@@ -10369,7 +10369,7 @@ pa_legitimate_constant_p (machine_mode mode, rtx x)
 
   if (TARGET_64BIT
       && HOST_BITS_PER_WIDE_INT > 32
-      && GET_CODE (x) == CONST_INT
+      && CONST_INT_P (x)
       && !reload_in_progress
       && !reload_completed
       && !LEGITIMATE_64BIT_CONST_INT_P (INTVAL (x))
@@ -10479,7 +10479,7 @@ pa_legitimate_address_p (machine_mode mode, rtx x, bool strict)
       else
 	return false;
 
-      if (GET_CODE (index) == CONST_INT)
+      if (CONST_INT_P (index))
 	{
 	  if (INT_5_BITS (index))
 	    return true;
@@ -10533,7 +10533,7 @@ pa_legitimate_address_p (machine_mode mode, rtx x, bool strict)
 	  && MODE_OK_FOR_SCALED_INDEXING_P (mode)
 	  && (strict ? STRICT_REG_OK_FOR_INDEX_P (XEXP (index, 0))
 		     : REG_OK_FOR_INDEX_P (XEXP (index, 0)))
-	  && GET_CODE (XEXP (index, 1)) == CONST_INT
+	  && CONST_INT_P (XEXP (index, 1))
 	  && INTVAL (XEXP (index, 1))
 	     == (HOST_WIDE_INT) GET_MODE_SIZE (mode)
 	  && borx_reg_operand (base, Pmode))
@@ -10570,7 +10570,7 @@ pa_legitimate_address_p (machine_mode mode, rtx x, bool strict)
       return false;
     }
 
-  if (GET_CODE (x) == CONST_INT && INT_5_BITS (x))
+  if (CONST_INT_P (x) && INT_5_BITS (x))
     return true;
 
   return false;
@@ -10617,7 +10617,7 @@ pa_legitimize_reload_address (rtx ad, machine_mode mode,
   if (optimize
       && GET_CODE (new_rtx) == PLUS
       && GET_CODE (XEXP (new_rtx, 0)) == REG
-      && GET_CODE (XEXP (new_rtx, 1)) == CONST_INT)
+      && CONST_INT_P (XEXP (new_rtx, 1)))
     {
       offset = INTVAL (XEXP ((new_rtx), 1));
 
diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h
index f38a6dce9f9..8de85da726d 100644
--- a/gcc/config/pa/pa.h
+++ b/gcc/config/pa/pa.h
@@ -768,7 +768,7 @@ extern int may_call_alloca;
 #define CONSTANT_ADDRESS_P(X) \
   ((GET_CODE (X) == LABEL_REF 						\
    || (GET_CODE (X) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (X))		\
-   || GET_CODE (X) == CONST_INT						\
+   || CONST_INT_P (X)						\
    || (GET_CODE (X) == CONST && !tls_referenced_p (X))			\
    || GET_CODE (X) == HIGH) 						\
    && (reload_in_progress || reload_completed				\
@@ -1246,7 +1246,7 @@ do {									     \
       fprintf (FILE, "0(%s)", reg_names [REGNO (addr)]);		\
       break;								\
     case PLUS:								\
-      gcc_assert (GET_CODE (XEXP (addr, 1)) == CONST_INT);		\
+      gcc_assert (CONST_INT_P (XEXP (addr, 1)));		\
       fprintf (FILE, "%d(%s)", (int)INTVAL (XEXP (addr, 1)),		\
 	       reg_names [REGNO (XEXP (addr, 0))]);			\
       break;								\
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 3867a55bca8..4174d590efb 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -3202,7 +3202,7 @@
         Else use the block move pattern.   */
 
   /* Undetermined size, use the library routine.  */
-  if (GET_CODE (operands[2]) != CONST_INT)
+  if (!CONST_INT_P (operands[2]))
     FAIL;
 
   size = INTVAL (operands[2]);
@@ -3390,7 +3390,7 @@
         Else use the block move pattern.   */
 
   /* Undetermined size, use the library routine.  */
-  if (GET_CODE (operands[2]) != CONST_INT)
+  if (!CONST_INT_P (operands[2]))
     FAIL;
 
   size = INTVAL (operands[2]);
@@ -3557,7 +3557,7 @@
     FAIL;
 
   /* Undetermined size, use the library routine.  */
-  if (GET_CODE (operands[1]) != CONST_INT)
+  if (!CONST_INT_P (operands[1]))
     FAIL;
 
   size = INTVAL (operands[1]);
@@ -3671,7 +3671,7 @@
     FAIL;
 
   /* Undetermined size, use the library routine.  */
-  if (GET_CODE (operands[1]) != CONST_INT)
+  if (!CONST_INT_P (operands[1]))
     FAIL;
 
   size = INTVAL (operands[1]);
@@ -4294,7 +4294,7 @@
   if (GET_CODE (operands[2]) == CONST_DOUBLE)
     operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
   else if (HOST_BITS_PER_WIDE_INT > 32
-	   && GET_CODE (operands[2]) == CONST_INT)
+	   && CONST_INT_P (operands[2]))
     operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffffffff);
   if (which_alternative == 1)
     output_asm_insn (\"copy %1,%0\", operands);
@@ -4556,7 +4556,7 @@
   [(set (match_operand:HI 0 "register_operand" "=r,r")
 	(zero_extend:HI
 	 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
-  "GET_CODE (operands[1]) != CONST_INT"
+  "!CONST_INT_P (operands[1])"
   "@
    {extru|extrw,u} %1,31,8,%0
    ldb%M1 %1,%0"
@@ -4574,7 +4574,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r,r")
 	(zero_extend:SI
 	 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
-  "GET_CODE (operands[1]) != CONST_INT"
+  "!CONST_INT_P (operands[1])"
   "@
    {extru|extrw,u} %1,31,8,%0
    ldb%M1 %1,%0"
@@ -4592,7 +4592,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r,r")
 	(zero_extend:SI
 	 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
-  "GET_CODE (operands[1]) != CONST_INT"
+  "!CONST_INT_P (operands[1])"
   "@
    {extru|extrw,u} %1,31,16,%0
    ldh%M1 %1,%0"
@@ -4610,7 +4610,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r,r")
 	(zero_extend:DI
 	 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
-  "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
+  "TARGET_64BIT && !CONST_INT_P (operands[1])"
   "@
    extrd,u %1,63,8,%0
    ldb%M1 %1,%0"
@@ -4628,7 +4628,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r,r")
 	(zero_extend:DI
 	 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
-  "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
+  "TARGET_64BIT && !CONST_INT_P (operands[1])"
   "@
    extrd,u %1,63,16,%0
    ldh%M1 %1,%0"
@@ -4646,7 +4646,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r,r")
 	(zero_extend:DI
 	 (match_operand:SI 1 "move_src_operand" "r,RQ")))]
-  "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
+  "TARGET_64BIT && !CONST_INT_P (operands[1])"
   "@
    extrd,u %1,63,32,%0
    ldw%M1 %1,%0"
@@ -4937,7 +4937,7 @@
   "!TARGET_64BIT"
   "*
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     {
       if (INTVAL (operands[2]) >= 0)
 	return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
@@ -5020,7 +5020,7 @@
   "!TARGET_64BIT"
   "*
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     {
       if (INTVAL (operands[2]) >= 0)
 	return \"addi %2,%R1,%R0\;{addco|add,c,tsv} %1,%%r0,%0\";
@@ -5152,7 +5152,7 @@
   "!TARGET_64BIT"
   "*
 {
-  if (GET_CODE (operands[1]) == CONST_INT)
+  if (CONST_INT_P (operands[1]))
     {
       if (INTVAL (operands[1]) >= 0)
 	return \"subi %1,%R2,%R0\;{subb|sub,b} %%r0,%2,%0\";
@@ -5211,7 +5211,7 @@
   "!TARGET_64BIT"
   "*
 {
-  if (GET_CODE (operands[1]) == CONST_INT)
+  if (CONST_INT_P (operands[1]))
     {
       if (INTVAL (operands[1]) >= 0)
 	return \"subi %1,%R2,%R0\;{subbo|sub,b,tsv} %%r0,%2,%0\";
@@ -5443,7 +5443,7 @@
       operands[5] = gen_rtx_REG (SImode, 31);
       operands[4] = gen_reg_rtx (SImode);
     }
-  if (GET_CODE (operands[2]) == CONST_INT && pa_emit_hpdiv_const (operands, 0))
+  if (CONST_INT_P (operands[2]) && pa_emit_hpdiv_const (operands, 0))
     DONE;
 }")
 
@@ -5504,7 +5504,7 @@
       operands[5] = gen_rtx_REG (SImode, 31);
       operands[4] = gen_reg_rtx (SImode);
     }
-  if (GET_CODE (operands[2]) == CONST_INT && pa_emit_hpdiv_const (operands, 1))
+  if (CONST_INT_P (operands[2]) && pa_emit_hpdiv_const (operands, 1))
     DONE;
 }")
 
@@ -6320,11 +6320,11 @@
   ""
   "
 {
-  if (GET_CODE (operands[2]) != CONST_INT)
+  if (!CONST_INT_P (operands[2]))
     {
       rtx temp = gen_reg_rtx (SImode);
       emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
-      if (GET_CODE (operands[1]) == CONST_INT)
+      if (CONST_INT_P (operands[1]))
 	emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
       else
 	emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
@@ -6419,11 +6419,11 @@
   "TARGET_64BIT"
   "
 {
-  if (GET_CODE (operands[2]) != CONST_INT)
+  if (!CONST_INT_P (operands[2]))
     {
       rtx temp = gen_reg_rtx (DImode);
       emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
-      if (GET_CODE (operands[1]) == CONST_INT)
+      if (CONST_INT_P (operands[1]))
 	emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
       else
 	emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
@@ -6518,7 +6518,7 @@
   ""
   "
 {
-  if (GET_CODE (operands[2]) != CONST_INT)
+  if (!CONST_INT_P (operands[2]))
     {
       rtx temp = gen_reg_rtx (SImode);
       emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
@@ -6553,7 +6553,7 @@
   "TARGET_64BIT"
   "
 {
-  if (GET_CODE (operands[2]) != CONST_INT)
+  if (!CONST_INT_P (operands[2]))
     {
       rtx temp = gen_reg_rtx (DImode);
       emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
@@ -6640,7 +6640,7 @@
   ""
   "*
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     {
       operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
       return \"{shd|shrpw} %1,%1,%2,%0\";
@@ -6658,7 +6658,7 @@
   ""
   "
 {
-  if (GET_CODE (operands[2]) != CONST_INT)
+  if (!CONST_INT_P (operands[2]))
     {
       rtx temp = gen_reg_rtx (SImode);
       emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
diff --git a/gcc/config/pa/predicates.md b/gcc/config/pa/predicates.md
index 90b578ed984..903fa82b858 100644
--- a/gcc/config/pa/predicates.md
+++ b/gcc/config/pa/predicates.md
@@ -254,7 +254,7 @@
     return false;
 
   if (REG_P (XEXP (op, 0)) && REG_OK_FOR_BASE_P (XEXP (op, 0)))
-    return GET_CODE (XEXP (op, 1)) == CONST_INT;
+    return CONST_INT_P (XEXP (op, 1));
 
   return false;
 })
@@ -631,7 +631,7 @@
 	      && ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
 		   && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
 		  || GET_CODE (XEXP (op, 0)) == LABEL_REF)
-	      && GET_CODE (XEXP (op, 1)) == CONST_INT);
+	      && CONST_INT_P (XEXP (op, 1)));
     default:
       break;
     }
diff --git a/gcc/config/pdp11/pdp11.c b/gcc/config/pdp11/pdp11.c
index 5f530a43000..53be7e7752a 100644
--- a/gcc/config/pdp11/pdp11.c
+++ b/gcc/config/pdp11/pdp11.c
@@ -910,7 +910,7 @@ print_operand_address (FILE *file, register rtx addr)
       break;
 
     default:
-      if (!again && GET_CODE (addr) == CONST_INT)
+      if (!again && CONST_INT_P (addr))
 	{
 	  /* Absolute (integer number) address.  */
 	  if (TARGET_DEC_ASM)
@@ -1122,7 +1122,7 @@ pdp11_rtx_costs (rtx x, machine_mode mode, int outer_code,
     }
   else if (code == PLUS || code == MINUS)
     {
-      if (GET_CODE (src) == CONST_INT &&
+      if (CONST_INT_P (src) &&
 	  (INTVAL (src) == 1 || INTVAL (src) == -1))
 	{
 	  *total += rtx_cost (dest, mode, (enum rtx_code) outer_code, 0, speed);
@@ -1835,7 +1835,7 @@ output_addr_const_pdp11 (FILE *file, rtx x)
 
     case PLUS:
       /* Some assemblers need integer constants to appear last (e.g. masm).  */
-      if (GET_CODE (XEXP (x, 0)) == CONST_INT)
+      if (CONST_INT_P (XEXP (x, 0)))
 	{
 	  output_addr_const_pdp11 (file, XEXP (x, 1));
 	  if (INTVAL (XEXP (x, 0)) >= 0)
@@ -1859,7 +1859,7 @@ output_addr_const_pdp11 (FILE *file, rtx x)
 	goto restart;
 
       output_addr_const_pdp11 (file, XEXP (x, 0));
-      if (GET_CODE (XEXP (x, 1)) != CONST_INT
+      if (!CONST_INT_P (XEXP (x, 1))
 	  || INTVAL (XEXP (x, 1)) >= 0)
 	fprintf (file, "-");
       output_addr_const_pdp11 (file, XEXP (x, 1));
diff --git a/gcc/config/pdp11/pdp11.md b/gcc/config/pdp11/pdp11.md
index be5ddc4c359..3b3815d19aa 100644
--- a/gcc/config/pdp11/pdp11.md
+++ b/gcc/config/pdp11/pdp11.md
@@ -1229,7 +1229,7 @@
   "reload_completed"
   "*
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     {
       if (INTVAL(operands[2]) == 1)
 	return \"inc\t%0\";
@@ -1417,7 +1417,7 @@
   "reload_completed"
   "*
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     {
       if (INTVAL(operands[2]) == 1)
 	return \"dec\t%0\";
@@ -1783,7 +1783,7 @@
         {
           r = gen_reg_rtx (<QHSint:mname>);
           emit_insn (gen_lshiftrt<mode>_sc (r, operands[1], const1_rtx));
-          if (GET_CODE (operands[2]) != CONST_INT)
+          if (!CONST_INT_P (operands[2]))
             {
               n = gen_reg_rtx (HImode);
               emit_insn (gen_addhi3 (n, operands [2], GEN_INT (-1)));
diff --git a/gcc/config/pru/pru.c b/gcc/config/pru/pru.c
index c764694f4f7..0cae5c5cfb7 100644
--- a/gcc/config/pru/pru.c
+++ b/gcc/config/pru/pru.c
@@ -2809,7 +2809,7 @@ pru_expand_delay_cycles (rtx arg)
 {
   HOST_WIDE_INT c, n;
 
-  if (GET_CODE (arg) != CONST_INT)
+  if (!CONST_INT_P (arg))
     {
       error ("%<__delay_cycles%> only takes constant arguments");
       return NULL_RTX;
diff --git a/gcc/config/pru/pru.md b/gcc/config/pru/pru.md
index 53fa73dec03..03527d7def8 100644
--- a/gcc/config/pru/pru.md
+++ b/gcc/config/pru/pru.md
@@ -230,7 +230,7 @@
 
   /* Support only loading a constant number of fixed-point registers from
      memory.  */
-  if (GET_CODE (operands[2]) != CONST_INT
+  if (!CONST_INT_P (operands[2])
       || GET_CODE (operands[1]) != MEM
       || GET_CODE (operands[0]) != REG)
     FAIL;
@@ -288,7 +288,7 @@
 
   /* Support only storing a constant number of fixed-point registers to
      memory.  */
-  if (GET_CODE (operands[2]) != CONST_INT
+  if (!CONST_INT_P (operands[2])
       || GET_CODE (operands[0]) != MEM
       || GET_CODE (operands[1]) != REG)
     FAIL;
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 431e90a8957..ca868a2ddca 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -1434,7 +1434,7 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
     {
       rtx reg;
 
-      if (GET_CODE (src) == CONST_INT)
+      if (CONST_INT_P (src))
 	{
 	  /* Apply the equivalent of PROMOTE_MODE here for constants to
 	     improve cse.  */
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 78260fcf6fd..edff6515354 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1557,7 +1557,7 @@
 	    (match_operand:QI 2 "arith_operand"    " rI")))]
   ""
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     operands[2] = GEN_INT (INTVAL (operands[2])
 			   & (GET_MODE_BITSIZE (SImode) - 1));
 
@@ -1612,7 +1612,7 @@
 	    (match_operand:QI 2 "arith_operand"    " rI")))]
   "TARGET_64BIT"
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     operands[2] = GEN_INT (INTVAL (operands[2])
 			   & (GET_MODE_BITSIZE (DImode) - 1));
 
@@ -1668,7 +1668,7 @@
 			  (match_operand:QI 2 "arith_operand"    " rI"))))]
   "TARGET_64BIT"
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
 
   return "<insn>%i2w\t%0,%1,%2";
diff --git a/gcc/config/rl78/rl78.c b/gcc/config/rl78/rl78.c
index d2caa118281..ada45f5bf54 100644
--- a/gcc/config/rl78/rl78.c
+++ b/gcc/config/rl78/rl78.c
@@ -940,7 +940,7 @@ characterize_address (rtx x, rtx *base, rtx *index, rtx *addend)
   /* We sometimes get these without the CONST wrapper */
   if (GET_CODE (x) == PLUS
       && GET_CODE (XEXP (x, 0)) == SYMBOL_REF
-      && GET_CODE (XEXP (x, 1)) == CONST_INT)
+      && CONST_INT_P (XEXP (x, 1)))
     {
       *addend = x;
       return true;
@@ -986,7 +986,7 @@ characterize_address (rtx x, rtx *base, rtx *index, rtx *addend)
     {
     case PLUS:
       if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
-	  && GET_CODE (XEXP (x, 0)) == CONST_INT)
+	  && CONST_INT_P (XEXP (x, 0)))
 	{
 	  *addend = x;
 	  return true;
@@ -2338,7 +2338,7 @@ rl78_peep_movhi_p (rtx *operands)
 	    a = XEXP (a, 0);
 	  if (GET_CODE (a) == PLUS)
 	    a = XEXP (a, 1);
-	  if (GET_CODE (a) == CONST_INT
+	  if (CONST_INT_P (a)
 	      && INTVAL (a) & 1)
 	    {
 #if DEBUG_PEEP
@@ -2995,7 +2995,7 @@ transcode_memory_rtx (rtx m, rtx newbase, rtx_insn *before)
   if (base == NULL_RTX)
     return m;
 
-  if (addendr && GET_CODE (addendr) == CONST_INT)
+  if (addendr && CONST_INT_P (addendr))
     addend = INTVAL (addendr);
 
   gcc_assert (REG_P (base));
@@ -3016,7 +3016,7 @@ transcode_memory_rtx (rtx m, rtx newbase, rtx_insn *before)
   if (addend < 0
       || (addend > limit && REGNO (newbase) != BC_REG)
       || (addendr
-	  && (GET_CODE (addendr) != CONST_INT)
+	  && (!CONST_INT_P (addendr))
 	  && ((REGNO (newbase) != BC_REG))
 	  ))
     {
@@ -4426,7 +4426,7 @@ rl78_rtx_costs (rtx          x,
 	case ASHIFT:
 	case ASHIFTRT:
 	case LSHIFTRT:
-	  if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+	  if (CONST_INT_P (XEXP (x, 1)))
 	    {
 	      switch (INTVAL (XEXP (x, 1)))
 		{
@@ -4484,7 +4484,7 @@ rl78_sfr_p (rtx x)
 {
   if (MEM_P (x))
     x = XEXP (x, 0);
-  if (GET_CODE (x) != CONST_INT)
+  if (!CONST_INT_P (x))
     return 0;
 
   if ((INTVAL (x) & 0xFF00) != 0xFF00)
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 4080c82c05f..1650adda137 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -13301,7 +13301,7 @@ rs6000_call_template_1 (rtx *operands, unsigned int funop, bool sibcall)
    else if (DEFAULT_ABI == ABI_DARWIN)
     {
       /* The cookie is in operand func+2.  */
-      gcc_checking_assert (GET_CODE (operands[funop + 2]) == CONST_INT);
+      gcc_checking_assert (CONST_INT_P (operands[funop + 2]));
       int cookie = INTVAL (operands[funop + 2]);
       if (cookie & CALL_LONG)
 	{
diff --git a/gcc/config/rx/rx.c b/gcc/config/rx/rx.c
index 0695f3b6538..905d3054de2 100644
--- a/gcc/config/rx/rx.c
+++ b/gcc/config/rx/rx.c
@@ -433,7 +433,7 @@ rx_print_operand_address (FILE * file, machine_mode /*mode*/, rtx addr)
 	    rx_print_operand (file, index, 'A');
 	    fprintf (file, ",");
 	  }
-	else /* GET_CODE (index) == CONST_INT  */
+	else /* CONST_INT_P (index)  */
 	  {
 	    rx_print_operand (file, index, 'A');
 	    fprintf (file, "[");
@@ -813,7 +813,7 @@ rx_print_operand (FILE * file, rtx op, int letter)
       else if (GET_CODE (op) == CONST
 	       && GET_CODE (XEXP (op, 0)) == PLUS
 	       && GET_CODE (XEXP (XEXP (op, 0), 0)) == UNSPEC
-	       && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
+	       && CONST_INT_P (XEXP (XEXP (op, 0), 1)))
 	{
 	  if (print_hash)
 	    fprintf (file, "#");
@@ -2585,7 +2585,7 @@ valid_psw_flag (rtx op, const char *which)
 {
   static int mvtc_inform_done = 0;
 
-  if (GET_CODE (op) == CONST_INT)
+  if (CONST_INT_P (op))
     switch (INTVAL (op))
       {
       case 0: case 'c': case 'C':
@@ -3476,7 +3476,7 @@ rx_adjust_insn_length (rtx_insn *insn, int current_length)
   gcc_checking_assert (REG_P (XEXP (XEXP (mem, 0), 0)));
 
   offset = XEXP (XEXP (mem, 0), 1);
-  gcc_checking_assert (GET_CODE (offset) == CONST_INT);
+  gcc_checking_assert (CONST_INT_P (offset));
 
   if (IN_RANGE (INTVAL (offset), 0, 255 * factor))
     return (zero && factor == 1) ? 3 : 4;
diff --git a/gcc/config/rx/rx.md b/gcc/config/rx/rx.md
index 9df73e6efc6..7065be69e43 100644
--- a/gcc/config/rx/rx.md
+++ b/gcc/config/rx/rx.md
@@ -1296,7 +1296,7 @@
    operands[5] = gen_reg_rtx (SImode);
    operands[6] = gen_rtx_SUBREG (GET_MODE (operands[0]), operands[3],
      TARGET_BIG_ENDIAN_DATA ? (GET_MODE (operands[0]) == HImode ? 2 : 3) : 0);
-   if (GET_CODE (operands[2]) != CONST_INT)
+   if (!CONST_INT_P (operands[2]))
      {
        emit_move_insn (operands[5], gen_rtx_ZERO_EXTEND (SImode, operands[2]));
        operands[2] = operands[5];
@@ -1320,7 +1320,7 @@
    operands[5] = gen_reg_rtx (SImode);
    operands[6] = gen_rtx_SUBREG (GET_MODE (operands[0]), operands[3],
      TARGET_BIG_ENDIAN_DATA ? (GET_MODE (operands[0]) == HImode ? 2 : 3) : 0);
-   if (GET_CODE (operands[2]) != CONST_INT)
+   if (!CONST_INT_P (operands[2]))
      {
        emit_move_insn (operands[5], gen_rtx_ZERO_EXTEND (SImode, operands[2]));
        operands[2] = operands[5];
diff --git a/gcc/config/s390/predicates.md b/gcc/config/s390/predicates.md
index fa15c05bcad..15758fb731a 100644
--- a/gcc/config/s390/predicates.md
+++ b/gcc/config/s390/predicates.md
@@ -173,7 +173,7 @@
   /* Allow adding *even* in-range constants.  */
   if (GET_CODE (op) == PLUS)
     {
-      if (GET_CODE (XEXP (op, 1)) != CONST_INT
+      if (!CONST_INT_P (XEXP (op, 1))
           || (INTVAL (XEXP (op, 1)) & 1) != 0)
         return false;
       if (INTVAL (XEXP (op, 1)) >= HOST_WIDE_INT_1 << 31
@@ -407,7 +407,7 @@
     off = 0;
   else if (GET_CODE (src_addr) == PLUS
 	   && GET_CODE (XEXP (src_addr, 0)) == REG
-	   && GET_CODE (XEXP (src_addr, 1)) == CONST_INT)
+	   && CONST_INT_P (XEXP (src_addr, 1)))
     {
       off = INTVAL (XEXP (src_addr, 1));
       src_addr = XEXP (src_addr, 0);
@@ -427,7 +427,7 @@
 	  || GET_MODE (SET_SRC (elt)) != elt_mode
 	  || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
 	  || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
-	  || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
+	  || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt), 0), 1))
 	  || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1))
 	     != off + i * GET_MODE_SIZE (elt_mode))
 	return false;
@@ -510,7 +510,7 @@
     off = 0;
   else if (GET_CODE (dest_addr) == PLUS
 	   && GET_CODE (XEXP (dest_addr, 0)) == REG
-	   && GET_CODE (XEXP (dest_addr, 1)) == CONST_INT)
+	   && CONST_INT_P (XEXP (dest_addr, 1)))
     {
       off = INTVAL (XEXP (dest_addr, 1));
       dest_addr = XEXP (dest_addr, 0);
@@ -530,7 +530,7 @@
 	  || GET_MODE (SET_DEST (elt)) != elt_mode
 	  || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
 	  || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
-	  || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
+	  || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt), 0), 1))
 	  || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1))
 	     != off + i * GET_MODE_SIZE (elt_mode))
 	return false;
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index 24b8a5c7a0d..c863514325a 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -1457,7 +1457,7 @@ s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
   int bit0, bit1;
 
   /* ??? Fixme: should work on CONST_WIDE_INT as well.  */
-  if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
+  if (!CONST_INT_P (op1) || !CONST_INT_P (op2))
     return VOIDmode;
 
   /* Selected bits all zero: CC0.
@@ -1499,7 +1499,7 @@ s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
 	if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
 	    && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
 	  return CCAPmode;
-	if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
+	if (GET_CODE (op0) == PLUS && CONST_INT_P (XEXP (op0, 1))
 	    && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
 	  return CCAPmode;
 	if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
@@ -1521,11 +1521,11 @@ s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
 	  }
 
 	if (register_operand (op0, HImode)
-	    && GET_CODE (op1) == CONST_INT
+	    && CONST_INT_P (op1)
 	    && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
 	  return CCT3mode;
 	if (register_operand (op0, QImode)
-	    && GET_CODE (op1) == CONST_INT
+	    && CONST_INT_P (op1)
 	    && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
 	  return CCT3mode;
 
@@ -1548,7 +1548,7 @@ s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
 	   constant the overflow behavior gets predictable. e.g.:
 	     int a, b; if ((b = a + c) > 0)
 	   with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP  */
-	if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
+	if (GET_CODE (op0) == PLUS && CONST_INT_P (XEXP (op0, 1))
 	    && (CONST_OK_FOR_K (INTVAL (XEXP (op0, 1)))
 		|| (CONST_OK_FOR_CONSTRAINT_P (INTVAL (XEXP (op0, 1)), 'O', "Os")
 		    /* Avoid INT32_MIN on 32 bit.  */
@@ -1569,7 +1569,7 @@ s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
       case UNGT:
       case LTGT:
 	if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
-	    && GET_CODE (op1) != CONST_INT)
+	    && !CONST_INT_P (op1))
 	  return CCSRmode;
 	return CCSmode;
 
@@ -1580,7 +1580,7 @@ s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
 	  return CCL1mode;
 
 	if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
-	    && GET_CODE (op1) != CONST_INT)
+	    && !CONST_INT_P (op1))
 	  return CCURmode;
 	return CCUmode;
 
@@ -1591,7 +1591,7 @@ s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
 	  return CCL2mode;
 
 	if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
-	    && GET_CODE (op1) != CONST_INT)
+	    && !CONST_INT_P (op1))
 	  return CCURmode;
 	return CCUmode;
 
@@ -1614,8 +1614,8 @@ s390_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
   if ((*code == EQ || *code == NE)
       && *op1 == const0_rtx
       && GET_CODE (*op0) == ZERO_EXTRACT
-      && GET_CODE (XEXP (*op0, 1)) == CONST_INT
-      && GET_CODE (XEXP (*op0, 2)) == CONST_INT
+      && CONST_INT_P (XEXP (*op0, 1))
+      && CONST_INT_P (XEXP (*op0, 2))
       && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
     {
       rtx inner = XEXP (*op0, 0);
@@ -1640,7 +1640,7 @@ s390_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
   if ((*code == EQ || *code == NE)
       && *op1 == const0_rtx
       && GET_CODE (*op0) == AND
-      && GET_CODE (XEXP (*op0, 1)) == CONST_INT
+      && CONST_INT_P (XEXP (*op0, 1))
       && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
     {
       rtx inner = XEXP (*op0, 0);
@@ -1673,7 +1673,7 @@ s390_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
 
   /* Narrow comparisons against 0xffff to HImode if possible.  */
   if ((*code == EQ || *code == NE)
-      && GET_CODE (*op1) == CONST_INT
+      && CONST_INT_P (*op1)
       && INTVAL (*op1) == 0xffff
       && SCALAR_INT_MODE_P (GET_MODE (*op0))
       && (nonzero_bits (*op0, GET_MODE (*op0))
@@ -2312,7 +2312,7 @@ s390_single_part (rtx op,
     = (HOST_WIDE_INT_1U << GET_MODE_BITSIZE (part_mode)) - 1;
   int i, part = -1;
 
-  if (GET_CODE (op) != CONST_INT)
+  if (!CONST_INT_P (op))
     return -1;
 
   for (i = 0; i < n_parts; i++)
@@ -2607,7 +2607,7 @@ s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
      overlapping.
      That's why we return false here although this may accept operations on
      overlapping memory areas.  */
-  if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
+  if (!addr_delta || !CONST_INT_P (addr_delta))
     return false;
 
   delta = INTVAL (addr_delta);
@@ -2798,7 +2798,7 @@ s390_short_displacement (rtx disp)
     return true;
 
   /* Integer displacement in range.  */
-  if (GET_CODE (disp) == CONST_INT)
+  if (CONST_INT_P (disp))
     return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
 
   /* GOT offset is not OK, the GOT can be large.  */
@@ -2946,14 +2946,14 @@ s390_decompose_address (rtx addr, struct s390_address *out)
   orig_disp = disp;
   if (disp)
     {
-      if (GET_CODE (disp) == CONST_INT)
+      if (CONST_INT_P (disp))
 	{
 	  offset = INTVAL (disp);
 	  disp = NULL_RTX;
 	}
       else if (GET_CODE (disp) == CONST
 	       && GET_CODE (XEXP (disp, 0)) == PLUS
-	       && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
+	       && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
 	{
 	  offset = INTVAL (XEXP (XEXP (disp, 0), 1));
 	  disp = XEXP (XEXP (disp, 0), 0);
@@ -3684,7 +3684,7 @@ s390_rtx_costs (rtx x, machine_mode mode, int outer_code,
 	  {
 	    rtx left = XEXP (x, 0);
 	    rtx right = XEXP (x, 1);
-	    if (GET_CODE (right) == CONST_INT
+	    if (CONST_INT_P (right)
 		&& CONST_OK_FOR_K (INTVAL (right)))
 	      *total = s390_cost->mhi;
 	    else if (GET_CODE (left) == SIGN_EXTEND)
@@ -3699,7 +3699,7 @@ s390_rtx_costs (rtx x, machine_mode mode, int outer_code,
 	    rtx right = XEXP (x, 1);
 	    if (TARGET_ZARCH)
 	      {
-		if (GET_CODE (right) == CONST_INT
+		if (CONST_INT_P (right)
 		    && CONST_OK_FOR_K (INTVAL (right)))
 		  *total = s390_cost->mghi;
 		else if (GET_CODE (left) == SIGN_EXTEND)
@@ -3854,8 +3854,8 @@ s390_rtx_costs (rtx x, machine_mode mode, int outer_code,
 	}
 
       if (GET_CODE (XEXP (x, 0)) == AND
-	  && GET_CODE (XEXP (x, 1)) == CONST_INT
-	  && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
+	  && CONST_INT_P (XEXP (x, 1))
+	  && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
 	{
 	  rtx op0 = XEXP (XEXP (x, 0), 0);
 	  rtx op1 = XEXP (XEXP (x, 0), 1);
@@ -4154,24 +4154,24 @@ bool
 legitimate_reload_constant_p (rtx op)
 {
   /* Accept la(y) operands.  */
-  if (GET_CODE (op) == CONST_INT
+  if (CONST_INT_P (op)
       && DISP_IN_RANGE (INTVAL (op)))
     return true;
 
   /* Accept l(g)hi/l(g)fi operands.  */
-  if (GET_CODE (op) == CONST_INT
+  if (CONST_INT_P (op)
       && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
     return true;
 
   /* Accept lliXX operands.  */
   if (TARGET_ZARCH
-      && GET_CODE (op) == CONST_INT
+      && CONST_INT_P (op)
       && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
       && s390_single_part (op, word_mode, HImode, 0) >= 0)
   return true;
 
   if (TARGET_EXTIMM
-      && GET_CODE (op) == CONST_INT
+      && CONST_INT_P (op)
       && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
       && s390_single_part (op, word_mode, SImode, 0) >= 0)
     return true;
@@ -4188,7 +4188,7 @@ legitimate_reload_constant_p (rtx op)
 
   /* Accept double-word operands that can be split.  */
   if (GET_CODE (op) == CONST_WIDE_INT
-      || (GET_CODE (op) == CONST_INT
+      || (CONST_INT_P (op)
 	  && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op)))
     {
       machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
@@ -4286,7 +4286,7 @@ s390_preferred_reload_class (rtx op, reg_class_t rclass)
 	   inheritance (see emit_input_reload_insns).  */
 	if (GET_CODE (XEXP (op, 0)) == PLUS
 	    && GET_CODE (XEXP (XEXP(op, 0), 0)) == SYMBOL_REF
-	    && GET_CODE (XEXP (XEXP(op, 0), 1)) == CONST_INT)
+	    && CONST_INT_P (XEXP (XEXP(op, 0), 1)))
 	  {
 	    if (flag_pic && reg_class_subset_p (ADDR_REGS, rclass))
 	      return ADDR_REGS;
@@ -4465,7 +4465,7 @@ s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
 	 displacements.  */
       if (MEM_P (x)
 	  && GET_CODE (XEXP (x, 0)) == PLUS
-	  && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
+	  && CONST_INT_P (XEXP (XEXP (x, 0), 1))
 	  && !SHORT_DISP_IN_RANGE(INTVAL (XEXP (XEXP (x, 0), 1)))
 	  && reg_class_subset_p (rclass, VEC_REGS)
 	  && (!reg_class_subset_p (rclass, FP_REGS)
@@ -4573,7 +4573,7 @@ s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
      a scratch register.  */
   if (MEM_P (x)
       && GET_CODE (XEXP (x, 0)) == PLUS
-      && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
+      && CONST_INT_P (XEXP (XEXP (x, 0), 1))
       && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
 			 + GET_MODE_SIZE (mode) - 1))
     {
@@ -4890,7 +4890,7 @@ legitimize_pic_address (rtx orig, rtx reg)
        || (GET_CODE (addr) == UNSPEC &&
 	   (XINT (addr, 1) == UNSPEC_GOTENT
 	    || XINT (addr, 1) == UNSPEC_PLT)))
-      && GET_CODE (addend) == CONST_INT)
+      && CONST_INT_P (addend))
     {
       /* This can be locally addressed.  */
 
@@ -5021,7 +5021,7 @@ legitimize_pic_address (rtx orig, rtx reg)
 	  new_rtx = reg;
 	}
     }
-  else if (GET_CODE (addr) == UNSPEC && GET_CODE (addend) == CONST_INT)
+  else if (GET_CODE (addr) == UNSPEC && CONST_INT_P (addend))
     {
       gcc_assert (XVECLEN (addr, 0) == 1);
       switch (XINT (addr, 1))
@@ -5066,7 +5066,7 @@ legitimize_pic_address (rtx orig, rtx reg)
       rtx base = legitimize_pic_address (addr, reg);
       new_rtx  = legitimize_pic_address (addend,
 					 base == reg ? NULL_RTX : reg);
-      if (GET_CODE (new_rtx) == CONST_INT)
+      if (CONST_INT_P (new_rtx))
 	new_rtx = plus_constant (Pmode, base, INTVAL (new_rtx));
       else
 	{
@@ -5264,7 +5264,7 @@ legitimize_tls_address (rtx addr, rtx reg)
     }
 
   else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
-	   && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
+	   && CONST_INT_P (XEXP (XEXP (addr, 0), 1)))
     {
       new_rtx = XEXP (XEXP (addr, 0), 0);
       if (GET_CODE (new_rtx) != SYMBOL_REF)
@@ -5352,7 +5352,7 @@ s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
      pointing into the stack frame, as the offsets will
      change later anyway.  */
 
-  if (GET_CODE (constant_term) == CONST_INT
+  if (CONST_INT_P (constant_term)
       && !TARGET_LONG_DISPLACEMENT
       && !DISP_IN_RANGE (INTVAL (constant_term))
       && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
@@ -5421,7 +5421,7 @@ legitimize_reload_address (rtx ad, machine_mode mode ATTRIBUTE_UNUSED,
 
   if (GET_CODE (ad) == PLUS
       && GET_CODE (XEXP (ad, 0)) == REG
-      && GET_CODE (XEXP (ad, 1)) == CONST_INT
+      && CONST_INT_P (XEXP (ad, 1))
       && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
     {
       HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
@@ -5453,7 +5453,7 @@ s390_expand_cpymem (rtx dst, rtx src, rtx len)
      do the right thing. Only for constant lengths below 64k we will
      generate inline code.  */
   if (s390_tune >= PROCESSOR_2097_Z10
-      && (GET_CODE (len) != CONST_INT || INTVAL (len) > (1<<16)))
+      && (!CONST_INT_P (len) || INTVAL (len) > (1<<16)))
     return false;
 
   /* Expand memcpy for constant length operands without a loop if it
@@ -5461,7 +5461,7 @@ s390_expand_cpymem (rtx dst, rtx src, rtx len)
 
      With a constant length argument a
      memcpy loop (without pfd) is 36 bytes -> 6 * mvc  */
-  if (GET_CODE (len) == CONST_INT
+  if (CONST_INT_P (len)
       && INTVAL (len) >= 0
       && INTVAL (len) <= 256 * 6
       && (!TARGET_MVCLE || INTVAL (len) <= 256))
@@ -5524,7 +5524,7 @@ s390_expand_cpymem (rtx dst, rtx src, rtx len)
       emit_label (loop_start_label);
 
       if (TARGET_Z10
-	  && (GET_CODE (len) != CONST_INT || INTVAL (len) > 768))
+	  && (!CONST_INT_P (len) || INTVAL (len) > 768))
 	{
 	  rtx prefetch;
 
@@ -5571,10 +5571,10 @@ s390_expand_cpymem (rtx dst, rtx src, rtx len)
 void
 s390_expand_setmem (rtx dst, rtx len, rtx val)
 {
-  if (GET_CODE (len) == CONST_INT && INTVAL (len) <= 0)
+  if (CONST_INT_P (len) && INTVAL (len) <= 0)
     return;
 
-  gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
+  gcc_assert (CONST_INT_P (val) || GET_MODE (val) == QImode);
 
   /* Expand setmem/clrmem for a constant length operand without a
      loop if it will be shorter that way.
@@ -5582,7 +5582,7 @@ s390_expand_setmem (rtx dst, rtx len, rtx val)
      clrmem loop (without PFD) is 24 bytes -> 4 * xc
      setmem loop (with PFD)    is 38 bytes -> ~4 * (mvi/stc + mvc)
      setmem loop (without PFD) is 32 bytes -> ~4 * (mvi/stc + mvc) */
-  if (GET_CODE (len) == CONST_INT
+  if (CONST_INT_P (len)
       && ((val == const0_rtx
 	   && (INTVAL (len) <= 256 * 4
 	       || (INTVAL (len) <= 256 * 5 && TARGET_SETMEM_PFD(val,len))))
@@ -5762,14 +5762,14 @@ s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
      do the right thing. Only for constant lengths below 64k we will
      generate inline code.  */
   if (s390_tune >= PROCESSOR_2097_Z10
-      && (GET_CODE (len) != CONST_INT || INTVAL (len) > (1<<16)))
+      && (!CONST_INT_P (len) || INTVAL (len) > (1<<16)))
     return false;
 
   /* As the result of CMPINT is inverted compared to what we need,
      we have to swap the operands.  */
   tmp = op0; op0 = op1; op1 = tmp;
 
-  if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
+  if (CONST_INT_P (len) && INTVAL (len) >= 0 && INTVAL (len) <= 256)
     {
       if (INTVAL (len) > 0)
 	{
@@ -5826,7 +5826,7 @@ s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
       emit_label (loop_start_label);
 
       if (TARGET_Z10
-	  && (GET_CODE (len) != CONST_INT || INTVAL (len) > 512))
+	  && (!CONST_INT_P (len) || INTVAL (len) > 512))
 	{
 	  rtx prefetch;
 
@@ -7417,7 +7417,7 @@ s390_delegitimize_address (rtx orig_x)
       y = XEXP (XEXP (x, 1), 0);
 
       if (GET_CODE (y) == PLUS
-	  && GET_CODE (XEXP (y, 1)) == CONST_INT)
+	  && CONST_INT_P (XEXP (y, 1)))
 	{
 	  offset = INTVAL (XEXP (y, 1));
 	  y = XEXP (y, 0);
@@ -8146,7 +8146,7 @@ static bool
 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
 {
   if (size == 8 && aligned_p
-      && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
+      && CONST_INT_P (x) && INTVAL (x) < INT_MIN)
     {
       fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
 	       INTVAL (x));
@@ -8349,7 +8349,7 @@ annotate_constant_pool_refs_1 (rtx *x)
 
       if (GET_CODE (memref) == CONST
 	  && GET_CODE (XEXP (memref, 0)) == PLUS
-	  && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
+	  && CONST_INT_P (XEXP (XEXP (memref, 0), 1))
 	  && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
 	  && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
 	{
@@ -8382,7 +8382,7 @@ annotate_constant_pool_refs_1 (rtx *x)
 
       if (GET_CODE (addrref) == CONST
 	  && GET_CODE (XEXP (addrref, 0)) == PLUS
-	  && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
+	  && CONST_INT_P (XEXP (XEXP (addrref, 0), 1))
 	  && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
 	  && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
 	{
@@ -8504,7 +8504,7 @@ replace_constant_pool_ref_1 (rtx *x, rtx ref, rtx offset)
     }
 
   if (GET_CODE (*x) == PLUS
-      && GET_CODE (XEXP (*x, 1)) == CONST_INT
+      && CONST_INT_P (XEXP (*x, 1))
       && GET_CODE (XEXP (*x, 0)) == UNSPEC
       && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
       && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
@@ -10076,7 +10076,7 @@ s390_optimize_nonescaping_tx (void)
 		  cc = XEXP (XEXP (ite, 0), 0);
 		  if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc))
 		      || GET_MODE (cc) != CCRAWmode
-		      || GET_CODE (XEXP (XEXP (ite, 0), 1)) != CONST_INT)
+		      || !CONST_INT_P (XEXP (XEXP (ite, 0), 1)))
 		    return;
 
 		  if (bb->succs->length () != 2)
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index e4516f6c378..a50090af0a1 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -2307,7 +2307,7 @@
   "GET_CODE (operands[1]) == SYMBOL_REF
    && CONSTANT_POOL_ADDRESS_P (operands[1])
    && get_pool_mode (operands[1]) == HImode
-   && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
+   && CONST_INT_P (get_pool_constant (operands[1]))"
   [(set (match_dup 0) (match_dup 2))]
   "operands[2] = get_pool_constant (operands[1]);")
 
@@ -2372,7 +2372,7 @@
   "GET_CODE (operands[1]) == SYMBOL_REF
    && CONSTANT_POOL_ADDRESS_P (operands[1])
    && get_pool_mode (operands[1]) == QImode
-   && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
+   && CONST_INT_P (get_pool_constant (operands[1]))"
   [(set (match_dup 0) (match_dup 2))]
   "operands[2] = get_pool_constant (operands[1]);")
 
@@ -2837,7 +2837,7 @@
 
   /* Support only loading a constant number of fixed-point registers from
      memory and only bother with this if more than two */
-  if (GET_CODE (operands[2]) != CONST_INT
+  if (!CONST_INT_P (operands[2])
       || INTVAL (operands[2]) < 2
       || INTVAL (operands[2]) > 16
       || GET_CODE (operands[1]) != MEM
@@ -2861,7 +2861,7 @@
 	}
       else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
 	       && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
-	       && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
+	       && CONST_INT_P (XEXP (XEXP (operands[1], 0), 1)))
 	{
 	  from = XEXP (XEXP (operands[1], 0), 0);
 	  off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
@@ -2928,7 +2928,7 @@
 
   /* Support only storing a constant number of fixed-point registers to
      memory and only bother with this if more than two.  */
-  if (GET_CODE (operands[2]) != CONST_INT
+  if (!CONST_INT_P (operands[2])
       || INTVAL (operands[2]) < 2
       || INTVAL (operands[2]) > 16
       || GET_CODE (operands[0]) != MEM
@@ -2953,7 +2953,7 @@
 	}
       else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
 	       && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
-	       && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
+	       && CONST_INT_P (XEXP (XEXP (operands[0], 0), 1)))
 	{
 	  to = XEXP (XEXP (operands[0], 0), 0);
 	  off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
@@ -6105,7 +6105,7 @@
 		 (match_operand:DI 2 "nonmemory_operand" "")))]
   "TARGET_64BIT"
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     {
       HOST_WIDE_INT c = INTVAL (operands[2]);
 
@@ -6131,7 +6131,7 @@
 		   (use (const_int 0))])]
   "!TARGET_64BIT"
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     {
       HOST_WIDE_INT c = INTVAL (operands[2]);
 
diff --git a/gcc/config/sparc/predicates.md b/gcc/config/sparc/predicates.md
index ee475800cfc..e19e8fdffb3 100644
--- a/gcc/config/sparc/predicates.md
+++ b/gcc/config/sparc/predicates.md
@@ -109,7 +109,7 @@
       return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
 		&& !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
 	       || GET_CODE (XEXP (op, 0)) == LABEL_REF)
-	      && GET_CODE (XEXP (op, 1)) == CONST_INT);
+	      && CONST_INT_P (XEXP (op, 1)));
 
     default:
       gcc_unreachable ();
@@ -275,7 +275,7 @@
   if (TARGET_ARCH64 || arith_simple_operand)
     return arith_simple_operand;
 
-  if (GET_CODE (op) != CONST_INT)
+  if (!CONST_INT_P (op))
     return false;
 
   m1 = trunc_int_for_mode (INTVAL (op), SImode);
@@ -397,7 +397,7 @@
 
   /* If 32-bit mode and this is a DImode constant, allow it
      so that the splits can be generated.  */
-  if (TARGET_ARCH32 && mode == DImode && GET_CODE (op) == CONST_INT)
+  if (TARGET_ARCH32 && mode == DImode && CONST_INT_P (op))
     return true;
 
   /* Allow FP constants to be built in integer registers.  */
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 0227a53861f..dc833072f8c 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -2258,7 +2258,7 @@ sparc_expand_move (machine_mode mode, rtx *operands)
 	  || (GET_CODE (operands[1]) == CONST
 	      && GET_CODE (XEXP (operands[1], 0)) == PLUS
 	      && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
-	      && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT
+	      && CONST_INT_P (XEXP (XEXP (operands[1], 0), 1))
 	      && can_use_mov_pic_label_ref (XEXP (XEXP (operands[1], 0), 0))))
 	{
 	  if (mode == SImode)
@@ -2373,7 +2373,7 @@ sparc_emit_set_const32 (rtx op0, rtx op1)
   if (can_create_pseudo_p ())
     temp = gen_reg_rtx (mode);
 
-  if (GET_CODE (op1) == CONST_INT)
+  if (CONST_INT_P (op1))
     {
       gcc_assert (!small_int_operand (op1, mode)
 		  && !const_high_operand (op1, mode));
@@ -2964,7 +2964,7 @@ sparc_emit_set_const64 (rtx op0, rtx op1)
   if (! can_create_pseudo_p ())
     temp = op0;
 
-  if (GET_CODE (op1) != CONST_INT)
+  if (!CONST_INT_P (op1))
     {
       sparc_emit_set_symbolic_const64 (op0, op1, temp);
       return;
@@ -3573,7 +3573,7 @@ emit_conditional_branch_insn (rtx operands[])
       && GET_CODE (operands[1]) == REG
       && (GET_MODE (operands[1]) == SImode
 	  || (TARGET_ARCH64 && GET_MODE (operands[1]) == DImode))
-      && (GET_CODE (operands[2]) != CONST_INT
+      && (!CONST_INT_P (operands[2])
 	  || SPARC_SIMM5_P (INTVAL (operands[2]))))
     {
       emit_cbcond_insn (GET_CODE (operands[0]), operands[1], operands[2], operands[3]);
@@ -4353,7 +4353,7 @@ pic_address_needs_scratch (rtx x)
   if (GET_CODE (x) == CONST
       && GET_CODE (XEXP (x, 0)) == PLUS
       && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
-      && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
+      && CONST_INT_P (XEXP (XEXP (x, 0), 1))
       && !SMALL_INT (XEXP (XEXP (x, 0), 1)))
     return 1;
 
@@ -4507,7 +4507,7 @@ sparc_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
 	   && GET_CODE (rs2) != MEM
 	   && !(GET_CODE (rs2) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs2))
 	   && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
-	   && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
+	   && (!CONST_INT_P (rs2) || SMALL_INT (rs2)))
 	  || ((REG_P (rs1)
 	       || GET_CODE (rs1) == SUBREG)
 	      && RTX_OK_FOR_OFFSET_P (rs2, mode)))
@@ -4575,7 +4575,7 @@ sparc_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
 	  && XEXP (rs1, 0) == imm1)
 	return 1;
     }
-  else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
+  else if (CONST_INT_P (addr) && SMALL_INT (addr))
     return 1;
   else
     return 0;
@@ -4827,7 +4827,7 @@ sparc_legitimize_tls_address (rtx addr)
       offset = XEXP (XEXP (addr, 0), 1);
 
       base = force_operand (base, NULL_RTX);
-      if (!(GET_CODE (offset) == CONST_INT && SMALL_INT (offset)))
+      if (!(CONST_INT_P (offset) && SMALL_INT (offset)))
 	offset = force_reg (Pmode, offset);
       ret = gen_rtx_PLUS (Pmode, base, offset);
     }
@@ -4933,7 +4933,7 @@ sparc_legitimize_pic_address (rtx orig, rtx reg)
       offset = sparc_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
 			 		     base == reg ? NULL_RTX : reg);
 
-      if (GET_CODE (offset) == CONST_INT)
+      if (CONST_INT_P (offset))
 	{
 	  if (SMALL_INT (offset))
 	    return plus_constant (Pmode, base, INTVAL (offset));
@@ -5046,7 +5046,7 @@ sparc_delegitimize_address (rtx x)
 		      || (GET_CODE (x) == CONST
 			  && GET_CODE (XEXP (x, 0)) == PLUS
 			  && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
-			  && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT));
+			  && CONST_INT_P (XEXP (XEXP (x, 0), 1))));
 	}
     }
 
@@ -5182,7 +5182,7 @@ mem_min_alignment (rtx mem, int desired)
 	     REG is aligned properly, the compiler will make
 	     sure any REG based index upon it will be so
 	     as well.  */
-	  if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
+	  if (CONST_INT_P (XEXP (addr, 1)))
 	    offset = XEXP (addr, 1);
 	  else
 	    offset = const0_rtx;
@@ -8910,7 +8910,7 @@ epilogue_renumber (register rtx *where, int test)
     case PLUS:
       if (GET_CODE (XEXP (*where, 0)) == REG
 	  && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
-	  && (GET_CODE (XEXP (*where, 1)) != CONST_INT
+	  && (!CONST_INT_P (XEXP (*where, 1))
 	      || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
 	return 1;
       break;
@@ -9166,7 +9166,7 @@ mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
 	{
           reg1 = REGNO (XEXP (addr1, 0));
 	  /* The offset must be constant!  */
-	  if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
+	  if (!CONST_INT_P (XEXP (addr1, 1)))
             return 0;
           offset1 = INTVAL (XEXP (addr1, 1));
 	}
@@ -9185,7 +9185,7 @@ mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
     return 0;
 
   if (GET_CODE (XEXP (addr2, 0)) != REG
-      || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
+      || !CONST_INT_P (XEXP (addr2, 1)))
     return 0;
 
   if (reg1 != REGNO (XEXP (addr2, 0)))
@@ -9341,7 +9341,7 @@ sparc_print_operand (FILE *file, rtx x, int code)
 
     case 'Y':
       /* Adjust the operand to take into account a RESTORE operation.  */
-      if (GET_CODE (x) == CONST_INT)
+      if (CONST_INT_P (x))
 	break;
       else if (GET_CODE (x) != REG)
 	output_operand_lossage ("invalid %%Y operand");
@@ -9596,7 +9596,7 @@ sparc_print_operand (FILE *file, rtx x, int code)
       {
 	/* Print a sign-extended 32-bit value.  */
 	HOST_WIDE_INT i;
-	if (GET_CODE(x) == CONST_INT)
+	if (CONST_INT_P (x))
 	  i = INTVAL (x);
 	else
 	  {
@@ -9741,7 +9741,7 @@ sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
 {
   /* ??? We only output .xword's for symbols and only then in environments
      where the assembler can handle them.  */
-  if (aligned_p && size == 8 && GET_CODE (x) != CONST_INT)
+  if (aligned_p && size == 8 && !CONST_INT_P (x))
     {
       if (TARGET_V9)
 	{
@@ -10314,7 +10314,7 @@ set_extends (rtx_insn *insn)
       {
 	rtx op0 = XEXP (SET_SRC (pat), 0);
 	rtx op1 = XEXP (SET_SRC (pat), 1);
-	if (GET_CODE (op1) == CONST_INT)
+	if (CONST_INT_P (op1))
 	  return INTVAL (op1) >= 0;
 	if (GET_CODE (op0) != REG)
 	  return 0;
@@ -10329,7 +10329,7 @@ set_extends (rtx_insn *insn)
 	rtx op1 = XEXP (SET_SRC (pat), 1);
 	if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
 	  return 0;
-	if (GET_CODE (op1) == CONST_INT)
+	if (CONST_INT_P (op1))
 	  return INTVAL (op1) >= 0;
 	return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
       }
@@ -10522,10 +10522,10 @@ output_v8plus_shift (rtx_insn *insn, rtx *operands, const char *opcode)
     operands[3] = operands[0];
 
   /* We can only shift by constants <= 63. */
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
 
-  if (GET_CODE (operands[1]) == CONST_INT)
+  if (CONST_INT_P (operands[1]))
     {
       output_asm_insn ("mov\t%1, %3", operands);
     }
@@ -10922,7 +10922,7 @@ static enum insn_code sparc_builtins_icode[(int) SPARC_BUILTIN_MAX];
 static int
 check_constant_argument (enum insn_code icode, int opnum, rtx opval)
 {
-  if (GET_CODE (opval) != CONST_INT)
+  if (!CONST_INT_P (opval))
     {
       error ("%qs expects a constant argument", insn_data[icode].name);
       return false;
@@ -12071,7 +12071,7 @@ sparc_rtx_costs (rtx x, machine_mode mode, int outer_code,
 	    {
 	      int nbits;
 
-	      if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+	      if (CONST_INT_P (XEXP (x, 1)))
 		{
 		  unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
 		  for (nbits = 0; value != 0; value &= value - 1)
@@ -13162,7 +13162,7 @@ output_v8plus_mult (rtx_insn *insn, rtx *operands, const char *opcode)
     output_asm_insn ("srl\t%L1, 0, %L1", operands);
   if (which_alternative == 1)
     output_asm_insn ("sllx\t%H1, 32, %H1", operands);
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     {
       if (which_alternative == 1)
 	{
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 7af62d599b9..14ce445d1e2 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -2551,8 +2551,8 @@ visl")
       rtx high_part = gen_highpart (SImode, operands[0]);
       rtx low_part = gen_lowpart (SImode, operands[0]);
 
-      gcc_assert (GET_CODE (hi) == CONST_INT);
-      gcc_assert (GET_CODE (lo) == CONST_INT);
+      gcc_assert (CONST_INT_P (hi));
+      gcc_assert (CONST_INT_P (lo));
 
       emit_move_insn_1 (high_part, hi);
 
@@ -3063,7 +3063,7 @@ visl")
 (define_insn "*zero_extendqihi2_insn"
   [(set (match_operand:HI 0 "register_operand" "=r,r")
 	(zero_extend:HI (match_operand:QI 1 "input_operand" "r,m")))]
-  "GET_CODE (operands[1]) != CONST_INT"
+  "!CONST_INT_P (operands[1])"
   "@
    and\t%1, 0xff, %0
    ldub\t%1, %0"
@@ -3080,7 +3080,7 @@ visl")
 (define_insn "*zero_extendqisi2_insn"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
 	(zero_extend:SI (match_operand:QI 1 "input_operand" "r,m")))]
-  "GET_CODE (operands[1]) != CONST_INT"
+  "!CONST_INT_P (operands[1])"
   "@
    and\t%1, 0xff, %0
    ldub\t%1, %0"
@@ -3097,7 +3097,7 @@ visl")
 (define_insn "*zero_extendqidi2_insn"
   [(set (match_operand:DI 0 "register_operand" "=r,r")
 	(zero_extend:DI (match_operand:QI 1 "input_operand" "r,m")))]
-  "TARGET_ARCH64 && GET_CODE (operands[1]) != CONST_INT"
+  "TARGET_ARCH64 && !CONST_INT_P (operands[1])"
   "@
    and\t%1, 0xff, %0
    ldub\t%1, %0"
@@ -3149,7 +3149,7 @@ visl")
   [(set (match_operand:DI 0 "register_operand" "=r,r,r")
 	(zero_extend:DI (match_operand:SI 1 "input_operand" "r,m,*f")))]
   "TARGET_ARCH64
-   && GET_CODE (operands[1]) != CONST_INT"
+   && !CONST_INT_P (operands[1])"
   "@
    srl\t%1, 0, %0
    lduw\t%1, %0
@@ -6488,7 +6488,7 @@ visl")
 		   (match_operand:SI 2 "arith_operand" "rI")))]
   ""
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
   return "sll\t%1, %2, %0";
 }
@@ -6502,7 +6502,7 @@ visl")
 {
   if (TARGET_ARCH32)
     {
-      if (GET_CODE (operands[2]) == CONST_INT)
+      if (CONST_INT_P (operands[2]))
 	FAIL;
       emit_insn (gen_ashldi3_v8plus (operands[0], operands[1], operands[2]));
       DONE;
@@ -6515,7 +6515,7 @@ visl")
 		   (match_operand:SI 2 "arith_operand" "rI")))]
   "TARGET_ARCH64"
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
   return "sllx\t%1, %2, %0";
 }
@@ -6559,7 +6559,7 @@ visl")
 		     (match_operand:SI 2 "arith_operand" "rI")))]
   ""
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
   return "sra\t%1, %2, %0";
 }
@@ -6571,7 +6571,7 @@ visl")
 				     (match_operand:SI 2 "arith_operand" "rI"))))]
   "TARGET_ARCH64"
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
   return "sra\t%1, %2, %0";
 }
@@ -6615,7 +6615,7 @@ visl")
 {
   if (TARGET_ARCH32)
     {
-      if (GET_CODE (operands[2]) == CONST_INT)
+      if (CONST_INT_P (operands[2]))
         FAIL;	/* prefer generic code in this case */
       emit_insn (gen_ashrdi3_v8plus (operands[0], operands[1], operands[2]));
       DONE;
@@ -6628,7 +6628,7 @@ visl")
 		     (match_operand:SI 2 "arith_operand" "rI")))]
   "TARGET_ARCH64"
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
   return "srax\t%1, %2, %0";
 }
@@ -6652,7 +6652,7 @@ visl")
 		     (match_operand:SI 2 "arith_operand" "rI")))]
   ""
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
   return "srl\t%1, %2, %0";
 }
@@ -6665,7 +6665,7 @@ visl")
 		       (match_operand:SI 2 "arith_operand" "rI"))))]
   "TARGET_ARCH64"
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
   return "srl\t%1, %2, %0";
 }
@@ -6681,7 +6681,7 @@ visl")
 		(match_operand 3 "const_int_operand" "")))]
   "TARGET_ARCH64 && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) == 0xffffffff"
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
   return "srl\t%1, %2, %0";
 }
@@ -6710,7 +6710,7 @@ visl")
 {
   if (TARGET_ARCH32)
     {
-      if (GET_CODE (operands[2]) == CONST_INT)
+      if (CONST_INT_P (operands[2]))
         FAIL;
       emit_insn (gen_lshrdi3_v8plus (operands[0], operands[1], operands[2]));
       DONE;
@@ -6723,7 +6723,7 @@ visl")
 		     (match_operand:SI 2 "arith_operand" "rI")))]
   "TARGET_ARCH64"
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
   return "srlx\t%1, %2, %0";
 }
@@ -6865,7 +6865,7 @@ visl")
 
   gcc_assert (MEM_P (operands[0]) && GET_MODE (operands[0]) == FUNCTION_MODE);
 
-  gcc_assert (GET_CODE (operands[3]) == CONST_INT);
+  gcc_assert (CONST_INT_P (operands[3]));
 
   if (GET_CODE (XEXP (operands[0], 0)) == LABEL_REF)
     {
@@ -6948,7 +6948,7 @@ visl")
    (match_operand 2 "immediate_operand" "")
    (clobber (reg:SI O7_REG))]
   ;;- Do not use operand 1 for most machines.
-  "TARGET_ARCH32 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 0"
+  "TARGET_ARCH32 && CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0"
 {
   operands[2] = GEN_INT (INTVAL (operands[2]) & 0xfff);
   return "call\t%a0, %1\n\t nop\n\tunimp\t%2";
@@ -6964,7 +6964,7 @@ visl")
    (match_operand 2 "immediate_operand" "")
    (clobber (reg:SI O7_REG))]
   ;;- Do not use operand 1 for most machines.
-  "TARGET_ARCH32 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 0"
+  "TARGET_ARCH32 && CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0"
 {
   operands[2] = GEN_INT (INTVAL (operands[2]) & 0xfff);
   return "call\t%a0, %1\n\t nop\n\tunimp\t%2";
@@ -6980,7 +6980,7 @@ visl")
    (match_operand 2 "immediate_operand" "")
    (clobber (reg:SI O7_REG))]
   ;;- Do not use operand 1 for most machines.
-  "TARGET_ARCH32 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0"
+  "TARGET_ARCH32 && CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0"
   "call\t%a0, %1\n\t nop\n\tnop"
   [(set_attr "type" "call_no_delay_slot")
    (set_attr "length" "3")])
@@ -6993,7 +6993,7 @@ visl")
    (match_operand 2 "immediate_operand" "")
    (clobber (reg:SI O7_REG))]
   ;;- Do not use operand 1 for most machines.
-  "TARGET_ARCH32 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0"
+  "TARGET_ARCH32 && CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0"
   "call\t%a0, %1\n\t nop\n\tnop"
   [(set_attr "type" "call_no_delay_slot")
    (set_attr "length" "3")])
@@ -8780,7 +8780,7 @@ visl")
    (clobber (match_scratch:SI 1 "=X,&h"))]
   "TARGET_VIS && TARGET_ARCH32"
 {
-  if (GET_CODE (operands[0]) == CONST_INT
+  if (CONST_INT_P (operands[0])
       || sparc_check_64 (operands[0], insn))
     return "wr\t%%g0, %0, %%gsr";
 
diff --git a/gcc/config/spu/constraints.md b/gcc/config/spu/constraints.md
index 6c6897d0602..2a542a7101e 100644
--- a/gcc/config/spu/constraints.md
+++ b/gcc/config/spu/constraints.md
@@ -161,7 +161,7 @@
 (define_memory_constraint "T"
   "Call operand, const_int, for absolute calls."
   (and (match_code "mem")
-       (match_test "GET_CODE (XEXP (op, 0)) == CONST_INT
+       (match_test "CONST_INT_P (XEXP (op, 0))
 		    && INTVAL (XEXP (op, 0)) >= 0
 		    && INTVAL (XEXP (op, 0)) <= 0x3ffff")))
 
diff --git a/gcc/config/spu/predicates.md b/gcc/config/spu/predicates.md
index 8d7767dad13..0d4314be398 100644
--- a/gcc/config/spu/predicates.md
+++ b/gcc/config/spu/predicates.md
@@ -65,7 +65,7 @@
   {
     if (spu_reg_operand (op, mode))
       return 1;
-    if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_VECTOR)
+    if (CONST_INT_P (op) || GET_CODE (op) == CONST_VECTOR)
       return arith_immediate_p (op, mode, -0x200, 0x1ff);
     return 0;
   })
@@ -75,7 +75,7 @@
   {
     if (spu_reg_operand (op, mode))
       return 1;
-    if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE
+    if (CONST_INT_P (op) || GET_CODE (op) == CONST_DOUBLE
 	|| GET_CODE (op) == CONST_VECTOR)
       return logical_immediate_p (op, mode);
     return 0;
@@ -86,7 +86,7 @@
   {
     if (spu_reg_operand (op, mode))
       return 1;
-    if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE
+    if (CONST_INT_P (op) || GET_CODE (op) == CONST_DOUBLE
 	|| GET_CODE (op) == CONST_VECTOR)
       return logical_immediate_p (op, mode)
 	     || iohl_immediate_p (op, mode);
diff --git a/gcc/config/spu/spu-builtins.md b/gcc/config/spu/spu-builtins.md
index 524324f22ab..fd56cdda586 100644
--- a/gcc/config/spu/spu-builtins.md
+++ b/gcc/config/spu/spu-builtins.md
@@ -28,10 +28,10 @@
 		        (const_int -16))))]
   ""
   {
-    if (GET_CODE (operands[2]) == CONST_INT
+    if (CONST_INT_P (operands[2])
 	&& (INTVAL (operands[2]) & 15) != 0)
       operands[2] = GEN_INT (INTVAL (operands[2]) & -16);
-    if (GET_CODE (operands[2]) != CONST_INT)
+    if (!CONST_INT_P (operands[2]))
       {
 	rtx op2 = operands[2];
 	operands[2] = force_reg (Pmode, operands[2]);
@@ -54,7 +54,7 @@
                         (const_int -16))))]
   ""
   {
-    if (GET_CODE (operands[1]) == CONST_INT
+    if (CONST_INT_P (operands[1])
 	&& (INTVAL (operands[1]) & 15) != 0)
       operands[1] = GEN_INT (INTVAL (operands[1]) & -16);
   })
@@ -73,10 +73,10 @@
         (match_operand:TI 0 "spu_reg_operand" "r,r"))]
   ""
   {
-    if (GET_CODE (operands[2]) == CONST_INT
+    if (CONST_INT_P (operands[2])
 	&& (INTVAL (operands[2]) & 15) != 0)
       operands[2] = GEN_INT (INTVAL (operands[2]) & -16);
-    if (GET_CODE (operands[2]) != CONST_INT)
+    if (!CONST_INT_P (operands[2]))
       {
 	rtx op2 = operands[2];
 	operands[2] = force_reg (Pmode, operands[2]);
@@ -99,7 +99,7 @@
         (match_operand:TI 0 "spu_reg_operand" "r"))]
   ""
   {
-    if (GET_CODE (operands[1]) == CONST_INT
+    if (CONST_INT_P (operands[1])
 	&& (INTVAL (operands[1]) & 15) != 0)
       operands[1] = GEN_INT (INTVAL (operands[1]) & -16);
   })
@@ -468,13 +468,13 @@
 		      (match_operand:SI 2 "spu_nonmem_operand")] 0 ))]
   ""
 {
-  if (GET_CODE (operands[2]) == CONST_INT
+  if (CONST_INT_P (operands[2])
       && (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) > 127))
     {
       error ("spu_convtf expects an integer literal in the range [0, 127].");
       operands[2] = force_reg (SImode, operands[2]);
     }
-  if (GET_CODE (operands[2]) != CONST_INT)
+  if (!CONST_INT_P (operands[2]))
     {
       rtx exp2;
       rtx cnv = gen_reg_rtx (V4SFmode);
@@ -501,14 +501,14 @@
   ""
 {
   rtx exp2;
-  if (GET_CODE (operands[2]) == CONST_INT
+  if (CONST_INT_P (operands[2])
       && (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) > 127))
     {
       error ("spu_convts expects an integer literal in the range [0, 127].");
       operands[2] = force_reg (SImode, operands[2]);
     }
   exp2 = spu_gen_exp2 (V4SFmode, operands[2]);
-  if (GET_CODE (operands[2]) != CONST_INT)
+  if (!CONST_INT_P (operands[2]))
     {
       rtx mul = gen_reg_rtx (V4SFmode);
       emit_insn (gen_mulv4sf3 (mul, operands[1], exp2));
@@ -525,13 +525,13 @@
 		      (match_operand:SI 2 "spu_nonmem_operand")] 0 ))]
   ""
 {
-  if (GET_CODE (operands[2]) == CONST_INT
+  if (CONST_INT_P (operands[2])
       && (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) > 127))
     {
       error ("spu_convtf expects an integer literal in the range [0, 127].");
       operands[2] = force_reg (SImode, operands[2]);
     }
-  if (GET_CODE (operands[2]) != CONST_INT)
+  if (!CONST_INT_P (operands[2]))
     {
       rtx exp2;
       rtx cnv = gen_reg_rtx (V4SFmode);
@@ -558,14 +558,14 @@
   ""
 {
   rtx exp2;
-  if (GET_CODE (operands[2]) == CONST_INT
+  if (CONST_INT_P (operands[2])
       && (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) > 127))
     {
       error ("spu_convtu expects an integer literal in the range [0, 127].");
       operands[2] = force_reg (SImode, operands[2]);
     }
   exp2 = spu_gen_exp2 (V4SFmode, operands[2]);
-  if (GET_CODE (operands[2]) != CONST_INT)
+  if (!CONST_INT_P (operands[2]))
     {
       rtx mul = gen_reg_rtx (V4SFmode);
       emit_insn (gen_mulv4sf3 (mul, operands[1], exp2));
diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c
index 613d30149c1..0e21e28b2e7 100644
--- a/gcc/config/spu/spu.c
+++ b/gcc/config/spu/spu.c
@@ -430,7 +430,7 @@ spu_expand_extv (rtx ops[], int unsignedp)
 	      emit_move_insn (mask, GEN_INT (-1));
 	      emit_insn (gen_rotqby_ti (s0, s0, r0));
 	      emit_insn (gen_rotqby_ti (s1, s1, r0));
-	      if (GET_CODE (r0) == CONST_INT)
+	      if (CONST_INT_P (r0))
 		r1 = GEN_INT (INTVAL (r0) & 15);
 	      else
 		emit_insn (gen_andsi3 (r1, r0, GEN_INT (15)));
@@ -603,8 +603,8 @@ spu_expand_block_move (rtx ops[])
   HOST_WIDE_INT bytes, align, offset;
   rtx src, dst, sreg, dreg, target;
   int i;
-  if (GET_CODE (ops[2]) != CONST_INT
-      || GET_CODE (ops[3]) != CONST_INT
+  if (!CONST_INT_P (ops[2])
+      || !CONST_INT_P (ops[3])
       || INTVAL (ops[2]) > (HOST_WIDE_INT) (MOVE_RATIO (optimize_insn_for_speed_p ()) * 8))
     return 0;
 
@@ -690,7 +690,7 @@ spu_emit_branch_or_set (int is_set, rtx cmp, rtx operands[])
 
   /* When op1 is a CONST_INT change (X >= C) to (X > C-1),
      and so on, to keep the constant in operand 1. */
-  if (GET_CODE (op1) == CONST_INT)
+  if (CONST_INT_P (op1))
     {
       HOST_WIDE_INT val = INTVAL (op1) - 1;
       if (trunc_int_for_mode (val, GET_MODE (op0)) == val)
@@ -719,7 +719,7 @@ spu_emit_branch_or_set (int is_set, rtx cmp, rtx operands[])
 
   /* However, if we generate an integer result, performing a reverse test
      would require an extra negation, so avoid that where possible.  */
-  if (GET_CODE (op1) == CONST_INT && is_set == 1)
+  if (CONST_INT_P (op1) && is_set == 1)
     {
       HOST_WIDE_INT val = INTVAL (op1) + 1;
       if (trunc_int_for_mode (val, GET_MODE (op0)) == val)
@@ -1037,7 +1037,7 @@ print_operand_address (FILE * file, register rtx addr)
   rtx offset;
 
   if (GET_CODE (addr) == AND
-      && GET_CODE (XEXP (addr, 1)) == CONST_INT
+      && CONST_INT_P (XEXP (addr, 1))
       && INTVAL (XEXP (addr, 1)) == -16)
     addr = XEXP (addr, 0);
 
@@ -1055,7 +1055,7 @@ print_operand_address (FILE * file, register rtx addr)
 	  fprintf (file, "%s,%s", reg_names[REGNO (reg)],
 		   reg_names[REGNO (offset)]);
 	}
-      else if (GET_CODE (offset) == CONST_INT)
+      else if (CONST_INT_P (offset))
 	{
 	  fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
 		   INTVAL (offset), reg_names[REGNO (reg)]);
@@ -1305,7 +1305,7 @@ print_operand (FILE * file, rtx x, int code)
       break;
 
     case 'M':			/* print code for c*d */
-      if (GET_CODE (x) == CONST_INT)
+      if (CONST_INT_P (x))
 	switch (INTVAL (x))
 	  {
 	  case 1:
@@ -3072,7 +3072,7 @@ int
 spu_constant_address_p (rtx x)
 {
   return (GET_CODE (x) == LABEL_REF || GET_CODE (x) == SYMBOL_REF
-	  || GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST
+	  || CONST_INT_P (x) || GET_CODE (x) == CONST
 	  || GET_CODE (x) == HIGH);
 }
 
@@ -3174,7 +3174,7 @@ classify_immediate (rtx op, machine_mode mode)
   if (!flag_pic
       && mode == V4SImode
       && GET_CODE (op) == CONST_VECTOR
-      && GET_CODE (CONST_VECTOR_ELT (op, 0)) != CONST_INT
+      && !CONST_INT_P (CONST_VECTOR_ELT (op, 0))
       && GET_CODE (CONST_VECTOR_ELT (op, 0)) != CONST_DOUBLE)
     op = unwrap_const_vec_duplicate (op);
 
@@ -3194,7 +3194,7 @@ classify_immediate (rtx op, machine_mode mode)
 	  rtx cst = XEXP (XEXP (op, 0), 1);
 
 	  if (GET_CODE (sym) == SYMBOL_REF
-	      && GET_CODE (cst) == CONST_INT
+	      && CONST_INT_P (cst)
 	      && satisfies_constraint_K (cst))
 	    return IC_IL1s;
 	}
@@ -3205,7 +3205,7 @@ classify_immediate (rtx op, machine_mode mode)
 
     case CONST_VECTOR:
       for (i = 0; i < GET_MODE_NUNITS (mode); i++)
-	if (GET_CODE (CONST_VECTOR_ELT (op, i)) != CONST_INT
+	if (!CONST_INT_P (CONST_VECTOR_ELT (op, i))
 	    && GET_CODE (CONST_VECTOR_ELT (op, i)) != CONST_DOUBLE)
 	  return IC_POOL;
       /* Fall through. */
@@ -3289,7 +3289,7 @@ const_vector_immediate_p (rtx x)
   int i;
   gcc_assert (GET_CODE (x) == CONST_VECTOR);
   for (i = 0; i < GET_MODE_NUNITS (GET_MODE (x)); i++)
-    if (GET_CODE (CONST_VECTOR_ELT (x, i)) != CONST_INT
+    if (!CONST_INT_P (CONST_VECTOR_ELT (x, i))
 	&& GET_CODE (CONST_VECTOR_ELT (x, i)) != CONST_DOUBLE)
       return 0;
   return 1;
@@ -3302,7 +3302,7 @@ logical_immediate_p (rtx op, machine_mode mode)
   unsigned char arr[16];
   int i, j;
 
-  gcc_assert (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE
+  gcc_assert (CONST_INT_P (op) || GET_CODE (op) == CONST_DOUBLE
 	      || GET_CODE (op) == CONST_VECTOR);
 
   if (GET_CODE (op) == CONST_VECTOR
@@ -3334,7 +3334,7 @@ iohl_immediate_p (rtx op, machine_mode mode)
   unsigned char arr[16];
   int i, j;
 
-  gcc_assert (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE
+  gcc_assert (CONST_INT_P (op) || GET_CODE (op) == CONST_DOUBLE
 	      || GET_CODE (op) == CONST_VECTOR);
 
   if (GET_CODE (op) == CONST_VECTOR
@@ -3366,7 +3366,7 @@ arith_immediate_p (rtx op, machine_mode mode,
   unsigned char arr[16];
   int bytes, i, j;
 
-  gcc_assert (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE
+  gcc_assert (CONST_INT_P (op) || GET_CODE (op) == CONST_DOUBLE
 	      || GET_CODE (op) == CONST_VECTOR);
 
   if (GET_CODE (op) == CONST_VECTOR
@@ -3407,7 +3407,7 @@ exp2_immediate_p (rtx op, machine_mode mode, int low, int high)
   unsigned char arr[16];
   int bytes, i, j;
 
-  gcc_assert (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE
+  gcc_assert (CONST_INT_P (op) || GET_CODE (op) == CONST_DOUBLE
 	      || GET_CODE (op) == CONST_VECTOR);
 
   if (GET_CODE (op) == CONST_VECTOR
@@ -3459,7 +3459,7 @@ ea_symbol_ref_p (const_rtx x)
       rtx plus = XEXP (x, 0);
       rtx op0 = XEXP (plus, 0);
       rtx op1 = XEXP (plus, 1);
-      if (GET_CODE (op1) == CONST_INT)
+      if (CONST_INT_P (op1))
 	x = op0;
     }
 
@@ -3518,7 +3518,7 @@ spu_legitimate_address_p (machine_mode mode,
   int aligned = GET_MODE_SIZE (mode) >= 16;
   if (aligned
       && GET_CODE (x) == AND
-      && GET_CODE (XEXP (x, 1)) == CONST_INT
+      && CONST_INT_P (XEXP (x, 1))
       && INTVAL (XEXP (x, 1)) == (HOST_WIDE_INT) - 16)
     x = XEXP (x, 0);
   switch (GET_CODE (x))
@@ -3557,7 +3557,7 @@ spu_legitimate_address_p (machine_mode mode,
 	  op1 = XEXP (op1, 0);
 	if (GET_CODE (op0) == REG
 	    && INT_REG_OK_FOR_BASE_P (op0, reg_ok_strict)
-	    && GET_CODE (op1) == CONST_INT
+	    && CONST_INT_P (op1)
 	    && ((INTVAL (op1) >= -0x2000 && INTVAL (op1) <= 0x1fff)
 		/* If virtual registers are involved, the displacement will
 		   change later on anyway, so checking would be premature.
@@ -4493,7 +4493,7 @@ spu_expand_mov (rtx * ops, machine_mode mode)
 
   /* Catch the SImode immediates greater than 0x7fffffff, and sign
      extend them. */
-  if (GET_CODE (ops[1]) == CONST_INT)
+  if (CONST_INT_P (ops[1]))
     {
       HOST_WIDE_INT val = trunc_int_for_mode (INTVAL (ops[1]), mode);
       if (val != INTVAL (ops[1]))
@@ -4575,7 +4575,7 @@ spu_expand_load (rtx dst0, rtx dst1, rtx src, int extra_rotby)
 	      rot = gen_reg_rtx (SImode);
 	      emit_insn (gen_addsi3 (rot, p0, p1));
 	    }
-	  else if (GET_CODE (p1) == CONST_INT && (INTVAL (p1) & 15))
+	  else if (CONST_INT_P (p1) && (INTVAL (p1) & 15))
 	    {
 	      if (INTVAL (p1) > 0
 		  && REG_POINTER (p0)
@@ -4602,7 +4602,7 @@ spu_expand_load (rtx dst0, rtx dst1, rtx src, int extra_rotby)
 	}
       else
 	{
-	  if (GET_CODE (p1) == CONST_INT && (INTVAL (p1) & 15))
+	  if (CONST_INT_P (p1) && (INTVAL (p1) & 15))
 	    {
 	      rot_amt = INTVAL (p1) & 15;
 	      if (INTVAL (p1) & -16)
@@ -4626,7 +4626,7 @@ spu_expand_load (rtx dst0, rtx dst1, rtx src, int extra_rotby)
     {
       if (GET_CODE (XEXP (addr, 0)) == PLUS
 	  && ALIGNED_SYMBOL_REF_P (XEXP (XEXP (addr, 0), 0))
-	  && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
+	  && CONST_INT_P (XEXP (XEXP (addr, 0), 1)))
 	{
 	  rot_amt = INTVAL (XEXP (XEXP (addr, 0), 1));
 	  if (rot_amt & -16)
@@ -4643,7 +4643,7 @@ spu_expand_load (rtx dst0, rtx dst1, rtx src, int extra_rotby)
 	  emit_move_insn (rot, addr);
 	}
     }
-  else if (GET_CODE (addr) == CONST_INT)
+  else if (CONST_INT_P (addr))
     {
       rot_amt = INTVAL (addr);
       addr = GEN_INT (rot_amt & -16);
@@ -4755,7 +4755,7 @@ spu_split_store (rtx * ops)
       aform = 0;
       p0 = XEXP (addr, 0);
       p1 = p1_lo = XEXP (addr, 1);
-      if (REG_P (p0) && GET_CODE (p1) == CONST_INT)
+      if (REG_P (p0) && CONST_INT_P (p1))
 	{
 	  p1_lo = GEN_INT (INTVAL (p1) & 15);
 	  if (reg_aligned_for_addr (p0))
@@ -4791,7 +4791,7 @@ spu_split_store (rtx * ops)
       else if (GET_CODE (addr) == CONST
 	       && GET_CODE (XEXP (addr, 0)) == PLUS
 	       && ALIGNED_SYMBOL_REF_P (XEXP (XEXP (addr, 0), 0))
-	       && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
+	       && CONST_INT_P (XEXP (XEXP (addr, 0), 1)))
 	{
 	  HOST_WIDE_INT v = INTVAL (XEXP (XEXP (addr, 0), 1));
 	  if ((v & -16) != 0)
@@ -4803,7 +4803,7 @@ spu_split_store (rtx * ops)
 	    addr = XEXP (XEXP (addr, 0), 0);
 	  p1_lo = GEN_INT (v & 15);
 	}
-      else if (GET_CODE (addr) == CONST_INT)
+      else if (CONST_INT_P (addr))
 	{
 	  p1_lo = GEN_INT (INTVAL (addr) & 15);
 	  addr = GEN_INT (INTVAL (addr) & -16);
@@ -4991,9 +4991,9 @@ gen_cpat_const (rtx * ops)
 {
   unsigned char dst[16];
   int i, offset, shift, isize;
-  if (GET_CODE (ops[3]) != CONST_INT
-      || GET_CODE (ops[2]) != CONST_INT
-      || (GET_CODE (ops[1]) != CONST_INT
+  if (!CONST_INT_P (ops[3])
+      || !CONST_INT_P (ops[2])
+      || (!CONST_INT_P (ops[1])
 	  && GET_CODE (ops[1]) != REG))
     return 0;
   if (GET_CODE (ops[1]) == REG
@@ -5029,7 +5029,7 @@ constant_to_array (machine_mode mode, rtx x, unsigned char arr[16])
 
   memset (arr, 0, 16);
   mode = GET_MODE (x) != VOIDmode ? GET_MODE (x) : mode;
-  if (GET_CODE (x) == CONST_INT
+  if (CONST_INT_P (x)
       || (GET_CODE (x) == CONST_DOUBLE
 	  && (mode == SFmode || mode == DFmode)))
     {
@@ -5076,7 +5076,7 @@ constant_to_array (machine_mode mode, rtx x, unsigned char arr[16])
       for (i = 0; i < units; i++)
 	{
 	  elt = CONST_VECTOR_ELT (x, i);
-	  if (GET_CODE (elt) == CONST_INT || GET_CODE (elt) == CONST_DOUBLE)
+	  if (CONST_INT_P (elt) || GET_CODE (elt) == CONST_DOUBLE)
 	    {
 	      if (GET_CODE (elt) == CONST_DOUBLE)
 		val = const_double_to_hwint (elt);
@@ -5309,7 +5309,7 @@ spu_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
 	REG ? COSTS_N_INSNS (12) : COSTS_N_INSNS (7);
       if (mode == SImode && GET_CODE (XEXP (x, 0)) == REG)
 	{
-	  if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+	  if (CONST_INT_P (XEXP (x, 1)))
 	    {
 	      HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
 	      cost = COSTS_N_INSNS (14);
@@ -5651,7 +5651,7 @@ void
 spu_builtin_splats (rtx ops[])
 {
   machine_mode mode = GET_MODE (ops[0]);
-  if (GET_CODE (ops[1]) == CONST_INT || GET_CODE (ops[1]) == CONST_DOUBLE)
+  if (CONST_INT_P (ops[1]) || GET_CODE (ops[1]) == CONST_DOUBLE)
     {
       unsigned char arr[16];
       constant_to_array (GET_MODE_INNER (mode), ops[1], arr);
@@ -5704,7 +5704,7 @@ spu_builtin_extract (rtx ops[])
 
   mode = GET_MODE (ops[1]);
 
-  if (GET_CODE (ops[2]) == CONST_INT)
+  if (CONST_INT_P (ops[2]))
     {
       switch (mode)
 	{
@@ -5769,7 +5769,7 @@ spu_builtin_insert (rtx ops[])
   rtx mask = gen_reg_rtx (TImode);
   rtx offset;
 
-  if (GET_CODE (ops[3]) == CONST_INT)
+  if (CONST_INT_P (ops[3]))
     offset = GEN_INT (INTVAL (ops[3]) * GET_MODE_SIZE (imode));
   else
     {
@@ -5798,7 +5798,7 @@ spu_builtin_promote (rtx ops[])
 
   emit_insn (gen_spu_convert (from, ops[1]));
 
-  if (GET_CODE (ops[2]) == CONST_INT)
+  if (CONST_INT_P (ops[2]))
     {
       pos = -GET_MODE_SIZE (imode) * INTVAL (ops[2]);
       if (GET_MODE_SIZE (imode) < 4)
@@ -6312,7 +6312,7 @@ spu_force_reg (machine_mode mode, rtx op)
   rtx x, r;
   if (GET_MODE (op) == VOIDmode || GET_MODE (op) == BLKmode)
     {
-      if ((SCALAR_INT_MODE_P (mode) && GET_CODE (op) == CONST_INT)
+      if ((SCALAR_INT_MODE_P (mode) && CONST_INT_P (op))
 	  || GET_MODE (op) == BLKmode)
 	return force_reg (mode, convert_to_mode (mode, op, 0));
       abort ();
@@ -6353,10 +6353,10 @@ spu_check_builtin_parm (struct spu_builtin_description *d, rtx op, int p)
 	  v = INTVAL (XEXP (XEXP (op, 0), 1));
 	  op = XEXP (XEXP (op, 0), 0);
 	}
-      else if (GET_CODE (op) == CONST_INT)
+      else if (CONST_INT_P (op))
 	v = INTVAL (op);
       else if (GET_CODE (op) == CONST_VECTOR
-	       && GET_CODE (CONST_VECTOR_ELT (op, 0)) == CONST_INT)
+	       && CONST_INT_P (CONST_VECTOR_ELT (op, 0)))
 	v = INTVAL (CONST_VECTOR_ELT (op, 0));
 
       /* The default for v is 0 which is valid in every range. */
@@ -6504,11 +6504,11 @@ spu_expand_builtin_1 (struct spu_builtin_description *d,
          si_ai(), we sometimes need to convert the scalar argument to a
          vector argument by splatting the scalar. */
       if (VECTOR_MODE_P (mode)
-	  && (GET_CODE (ops[i]) == CONST_INT
+	  && (CONST_INT_P (ops[i])
 	      || GET_MODE_CLASS (GET_MODE (ops[i])) == MODE_INT
 	      || GET_MODE_CLASS (GET_MODE (ops[i])) == MODE_FLOAT))
 	{
-	  if (GET_CODE (ops[i]) == CONST_INT)
+	  if (CONST_INT_P (ops[i]))
 	    ops[i] = spu_const (mode, INTVAL (ops[i]));
 	  else
 	    {
@@ -6960,8 +6960,8 @@ rtx
 spu_gen_exp2 (machine_mode mode, rtx scale)
 {
   gcc_assert (mode == V4SFmode);
-  gcc_assert (GET_MODE (scale) == SImode || GET_CODE (scale) == CONST_INT);
-  if (GET_CODE (scale) != CONST_INT)
+  gcc_assert (GET_MODE (scale) == SImode || CONST_INT_P (scale));
+  if (!CONST_INT_P (scale))
     {
       /* unsigned int exp = (127 + scale) << 23;
 	__vector float m = (__vector float) spu_splats (exp); */
diff --git a/gcc/config/spu/spu.md b/gcc/config/spu/spu.md
index bb622981abd..ba7858a645f 100644
--- a/gcc/config/spu/spu.md
+++ b/gcc/config/spu/spu.md
@@ -1440,7 +1440,7 @@
     rtx b = operands[4];
     rtx c = operands[5];
     rtx d = operands[6];
-    if (GET_CODE(operands[2]) == CONST_INT)
+    if (CONST_INT_P (operands[2]))
       {
 	val = INTVAL(operands[2]);
 	emit_move_insn(d, operands[2]);
@@ -2378,7 +2378,7 @@
 			      (match_operand:SI 2 "spu_nonmem_operand" "")))
 	      (clobber (match_dup:TI 3))])]
   ""
-  "if (GET_CODE (operands[2]) == CONST_INT)
+  "if (CONST_INT_P (operands[2]))
     {
       emit_insn (gen_ashlti3_imm(operands[0], operands[1], operands[2]));
       DONE;
@@ -2515,7 +2515,7 @@
 		      (match_dup:SI 5)))]
   {
     operands[3] = gen_reg_rtx (<MODE>mode);
-    if (GET_CODE (operands[2]) == CONST_INT)
+    if (CONST_INT_P (operands[2]))
       {
 	HOST_WIDE_INT val = INTVAL(operands[2]);
 	operands[4] = GEN_INT (val & 7);
@@ -2541,7 +2541,7 @@
 			      (const_int -8))))]
   ""
   {
-    if (GET_CODE (operands[2]) == CONST_INT)
+    if (CONST_INT_P (operands[2]))
       operands[2] = GEN_INT (7 - INTVAL (operands[2]));
     else
       {
@@ -2576,7 +2576,7 @@
 	(lshiftrt:DTI (match_dup:DTI 1)
 		      (and:SI (neg:SI (match_dup:SI 3)) (const_int 7))))]
   {
-    if (GET_CODE (operands[2]) == CONST_INT)
+    if (CONST_INT_P (operands[2]))
       operands[3] = GEN_INT (-INTVAL (operands[2]));
     else
       emit_insn (gen_subsi3 (operands[3], GEN_INT (0), operands[2]));
@@ -2601,7 +2601,7 @@
 			       (const_int 8))))]
   ""
   {
-    if (GET_CODE (operands[2]) == CONST_INT)
+    if (CONST_INT_P (operands[2]))
       operands[2] = GEN_INT (-INTVAL (operands[2]));
     else
       {
@@ -2685,13 +2685,13 @@
     rtx op4 = operands[4];
     rtx op5 = operands[5];
 
-    if (GET_CODE (op2) == CONST_INT && INTVAL (op2) >= 63)
+    if (CONST_INT_P (op2) && INTVAL (op2) >= 63)
       {
 	rtx op0s = gen_rtx_REG (SImode, REGNO (op0));
 	emit_insn (gen_ashrsi3 (op0s, op1s, GEN_INT (32)));
 	emit_insn (gen_spu_fsm (op0v, op0s));
       }
-    else if (GET_CODE (op2) == CONST_INT && INTVAL (op2) >= 32)
+    else if (CONST_INT_P (op2) && INTVAL (op2) >= 32)
       {
 	rtx op0d = gen_rtx_REG (V2DImode, REGNO (op0));
 	HOST_WIDE_INT val = INTVAL (op2);
diff --git a/gcc/config/stormy16/predicates.md b/gcc/config/stormy16/predicates.md
index c8928c706d0..e5a653ac5a7 100644
--- a/gcc/config/stormy16/predicates.md
+++ b/gcc/config/stormy16/predicates.md
@@ -73,7 +73,7 @@
     op = XEXP (XEXP (op, 0), 0);
   else
     return 0;
-  if (GET_CODE (op) == CONST_INT)
+  if (CONST_INT_P (op))
     {
       HOST_WIDE_INT i = INTVAL (op);
       return (i >= 0x7f00 && i < 0x7fff);
@@ -107,7 +107,7 @@
   (match_code "const_int")
 {
   HOST_WIDE_INT i;
-  if (GET_CODE (op) != CONST_INT)
+  if (!CONST_INT_P (op))
     return 0;
   i = ~ INTVAL (op);
   if (mode == QImode)
@@ -123,7 +123,7 @@
   (match_code "const_int")
 {
   HOST_WIDE_INT i;
-  if (GET_CODE (op) != CONST_INT)
+  if (!CONST_INT_P (op))
     return 0;
   i = INTVAL (op);
   if (mode == QImode)
@@ -147,7 +147,7 @@
 (define_predicate "xstormy16_carry_plus_operand"
   (match_code "plus")
 {
-  return (GET_CODE (XEXP (op, 1)) == CONST_INT
+  return (CONST_INT_P (XEXP (op, 1))
 	  && (INTVAL (XEXP (op, 1)) < -4 || INTVAL (XEXP (op, 1)) > 4));
 })
 
diff --git a/gcc/config/v850/predicates.md b/gcc/config/v850/predicates.md
index 0de83623b5d..d662ad0308d 100644
--- a/gcc/config/v850/predicates.md
+++ b/gcc/config/v850/predicates.md
@@ -22,7 +22,7 @@
 (define_predicate "reg_or_0_operand"
   (match_code "reg,subreg,const_int,const_double")
 {
-  if (GET_CODE (op) == CONST_INT)
+  if (CONST_INT_P (op))
     return INTVAL (op) == 0;
 
   else if (GET_CODE (op) == CONST_DOUBLE)
@@ -38,7 +38,7 @@
 (define_predicate "reg_or_int5_operand"
   (match_code "reg,subreg,const_int")
 {
-  if (GET_CODE (op) == CONST_INT)
+  if (CONST_INT_P (op))
     return CONST_OK_FOR_J (INTVAL (op));
 
   else
@@ -51,7 +51,7 @@
 (define_predicate "reg_or_int9_operand"
   (match_code "reg,subreg,const_int")
 {
-  if (GET_CODE (op) == CONST_INT)
+  if (CONST_INT_P (op))
     return CONST_OK_FOR_O (INTVAL (op));
 
   return register_operand (op, mode);
@@ -62,7 +62,7 @@
 (define_predicate "reg_or_const_operand"
   (match_code "reg,const_int")
 {
-  if (GET_CODE (op) == CONST_INT)
+  if (CONST_INT_P (op))
     return TRUE;
 
   return register_operand (op, mode);
@@ -99,7 +99,7 @@
      must be done with HIGH & LO_SUM patterns.  */
   if (CONSTANT_P (op)
       && GET_CODE (op) != HIGH
-      && !(GET_CODE (op) == CONST_INT
+      && !(CONST_INT_P (op)
            && (CONST_OK_FOR_J (INTVAL (op))
                || CONST_OK_FOR_K (INTVAL (op))
                || CONST_OK_FOR_L (INTVAL (op)))))
@@ -114,7 +114,7 @@
 (define_predicate "disp23_operand"
   (match_code "const_int")
 {
-  if (GET_CODE (op) == CONST_INT
+  if (CONST_INT_P (op)
       && ((unsigned)(INTVAL (op)) >= 0x8000)
       && ((unsigned)(INTVAL (op)) < 0x400000))
     return 1;
@@ -145,7 +145,7 @@
 (define_predicate "power_of_two_operand"
   (match_code "const_int")
 {
-  if (GET_CODE (op) != CONST_INT)
+  if (!CONST_INT_P (op))
     return 0;
 
   if (exact_log2 (INTVAL (op)) == -1)
@@ -209,7 +209,7 @@
 	  || GET_CODE (XEXP (plus, 0)) != REG
 	  || GET_MODE (XEXP (plus, 0)) != SImode
 	  || REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
-	  || GET_CODE (XEXP (plus, 1)) != CONST_INT)
+	  || !CONST_INT_P (XEXP (plus, 1)))
 	return 0;
 
       /* If the register is being pushed somewhere other than the stack
@@ -296,7 +296,7 @@
 	  || GET_CODE (XEXP (plus, 0)) != REG
 	  || GET_MODE (XEXP (plus, 0)) != SImode
 	  || REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
-	  || GET_CODE (XEXP (plus, 1)) != CONST_INT)
+	  || !CONST_INT_P (XEXP (plus, 1)))
 	return 0;
     }
 
@@ -368,7 +368,7 @@
 	  || GET_CODE (XEXP (plus, 0)) != REG
 	  || GET_MODE (XEXP (plus, 0)) != SImode
 	  || REGNO    (XEXP (plus, 0)) != STACK_POINTER_REGNUM
-	  || GET_CODE (XEXP (plus, 1)) != CONST_INT)
+	  || !CONST_INT_P (XEXP (plus, 1)))
 	return 0;
     }
 
@@ -433,7 +433,7 @@
 	  || GET_CODE (XEXP (plus, 0)) != REG
 	  || GET_MODE (XEXP (plus, 0)) != SImode
 	  || REGNO    (XEXP (plus, 0)) != STACK_POINTER_REGNUM
-	  || GET_CODE (XEXP (plus, 1)) != CONST_INT)
+	  || !CONST_INT_P (XEXP (plus, 1)))
 	return 0;
 
       /* If the register is being pushed somewhere other than the stack
@@ -464,7 +464,7 @@
   else
     return 0;
 
-  if (GET_CODE (op) != CONST_INT)
+  if (!CONST_INT_P (op))
     return 0;
 
   if (exact_log2 (~INTVAL (op) & mask) == -1)
diff --git a/gcc/config/v850/v850.c b/gcc/config/v850/v850.c
index cca24edb3ae..bf9fbea608d 100644
--- a/gcc/config/v850/v850.c
+++ b/gcc/config/v850/v850.c
@@ -373,7 +373,7 @@ v850_rtx_costs (rtx x, machine_mode mode, int outer_code,
         {
 	  if (GET_CODE (XEXP (x, 1)) == REG)
 	    *total = 4;
-	  else if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+	  else if (CONST_INT_P (XEXP (x, 1)))
 	    {
 	      if (CONST_OK_FOR_O (INTVAL (XEXP (x, 1))))
 	        *total = 6;
@@ -554,7 +554,7 @@ v850_print_operand (FILE * file, rtx x, int code)
 	    machine_mode mode = GET_MODE (x);
 	    x = XEXP (adjust_address (x, SImode, 4), 0);
 	    v850_print_operand_address (file, mode, x);
-	    if (GET_CODE (x) == CONST_INT)
+	    if (CONST_INT_P (x))
 	      fprintf (file, "[r0]");
 	  }
 	  break;
@@ -629,7 +629,7 @@ v850_print_operand (FILE * file, rtx x, int code)
       switch (GET_CODE (x))
 	{
 	case MEM:
-	  if (GET_CODE (XEXP (x, 0)) == CONST_INT)
+	  if (CONST_INT_P (XEXP (x, 0)))
 	    output_address (GET_MODE (x),
 			    gen_rtx_PLUS (SImode, gen_rtx_REG (SImode, 0),
 					  XEXP (x, 0)));
@@ -823,7 +823,7 @@ output_move_single (rtx * operands)
       if (REG_P (src))
 	return "mov %1,%0";
 
-      else if (GET_CODE (src) == CONST_INT)
+      else if (CONST_INT_P (src))
 	{
 	  HOST_WIDE_INT value = INTVAL (src);
 
@@ -898,7 +898,7 @@ output_move_single (rtx * operands)
       if (REG_P (src))
 	return "%S0st%W0 %1,%0";
 
-      else if (GET_CODE (src) == CONST_INT && INTVAL (src) == 0)
+      else if (CONST_INT_P (src) && INTVAL (src) == 0)
 	return "%S0st%W0 %.,%0";
 
       else if (GET_CODE (src) == CONST_DOUBLE
@@ -1091,7 +1091,7 @@ ep_memory_operand (rtx op, machine_mode mode, int unsigned_load)
     case PLUS:
       op0 = XEXP (addr, 0);
       op1 = XEXP (addr, 1);
-      if (GET_CODE (op1) == CONST_INT
+      if (CONST_INT_P (op1)
 	  && INTVAL (op1) < max_offset
 	  && INTVAL (op1) >= 0
 	  && (INTVAL (op1) & mask) == 0)
@@ -1186,7 +1186,7 @@ Saved %d bytes (%d uses of register %s) in function %s, starting as insn %d, end
 		  else if (GET_CODE (addr) == PLUS
 			   && GET_CODE (XEXP (addr, 0)) == REG
 			   && REGNO (XEXP (addr, 0)) == (unsigned) regno
-			   && GET_CODE (XEXP (addr, 1)) == CONST_INT
+			   && CONST_INT_P (XEXP (addr, 1))
 			   && ((INTVAL (XEXP (addr, 1)))
 			       < ep_memory_offset (GET_MODE (*p_mem),
 						   unsignedp))
@@ -1349,7 +1349,7 @@ v850_reorg (void)
 
 		  else if (GET_CODE (addr) == PLUS
 			   && GET_CODE (XEXP (addr, 0)) == REG
-			   && GET_CODE (XEXP (addr, 1)) == CONST_INT
+			   && CONST_INT_P (XEXP (addr, 1))
 			   && ((INTVAL (XEXP (addr, 1)))
 			       < ep_memory_offset (GET_MODE (mem), unsignedp))
 			   && ((INTVAL (XEXP (addr, 1))) >= 0))
@@ -2217,7 +2217,7 @@ construct_restore_jr (rtx op)
      registers.  */
   gcc_assert (GET_CODE (XVECEXP (op, 0, 1)) == SET);
   gcc_assert (GET_CODE (SET_SRC (XVECEXP (op, 0, 1))) == PLUS);
-  gcc_assert (GET_CODE (XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1)) == CONST_INT);
+  gcc_assert (CONST_INT_P (XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1)));
     
   stack_bytes = INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1));
 
@@ -2322,7 +2322,7 @@ construct_save_jarl (rtx op)
   gcc_assert (GET_CODE (XVECEXP (op, 0, 0)) == SET);
   gcc_assert (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) == PLUS);
   gcc_assert (GET_CODE (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0)) == REG);
-  gcc_assert (GET_CODE (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)) == CONST_INT);
+  gcc_assert (CONST_INT_P (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)));
     
   /* Work out how many bytes to push onto the stack after storing the
      registers.  */
@@ -2620,7 +2620,7 @@ construct_dispose_instruction (rtx op)
      stack before retrieving registers.  */
   gcc_assert (GET_CODE (XVECEXP (op, 0, 1)) == SET);
   gcc_assert (GET_CODE (SET_SRC (XVECEXP (op, 0, 1))) == PLUS);
-  gcc_assert (GET_CODE (XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1)) == CONST_INT);
+  gcc_assert (CONST_INT_P (XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1)));
     
   stack_bytes = INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1));
 
@@ -2741,7 +2741,7 @@ construct_prepare_instruction (rtx op)
      the stack after storing the registers.  */
   gcc_assert (GET_CODE (XVECEXP (op, 0, 0)) == SET);
   gcc_assert (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) == PLUS);
-  gcc_assert (GET_CODE (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)) == CONST_INT);
+  gcc_assert (CONST_INT_P (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)));
     
   stack_bytes = INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1));
 
@@ -3024,7 +3024,7 @@ v850_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
 	  || !(GET_CODE (x) == CONST
 	       && GET_CODE (XEXP (x, 0)) == PLUS
 	       && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
-	       && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
+	       && CONST_INT_P (XEXP (XEXP (x, 0), 1))
 	       && !CONST_OK_FOR_K (INTVAL (XEXP (XEXP (x, 0), 1)))));
 }
 
diff --git a/gcc/config/v850/v850.md b/gcc/config/v850/v850.md
index 112ce9b0d5f..167d87ca60b 100644
--- a/gcc/config/v850/v850.md
+++ b/gcc/config/v850/v850.md
@@ -255,7 +255,7 @@
 	&& GET_CODE (operands[1]) != HIGH
 	&& ! (TARGET_V850E_UP)
 	&& !special_symbolref_operand (operands[1], VOIDmode)
-	&& !(GET_CODE (operands[1]) == CONST_INT
+	&& !(CONST_INT_P (operands[1])
 	     && (CONST_OK_FOR_J (INTVAL (operands[1]))
 		 || CONST_OK_FOR_K (INTVAL (operands[1]))
 		 || CONST_OK_FOR_L (INTVAL (operands[1])))))
@@ -590,7 +590,7 @@
 	  (sign_extend:SI (match_operand:HI 2 "nonmemory_operand" ""))))]
   ""
   {
-    if (GET_CODE (operands[2]) == CONST_INT)
+    if (CONST_INT_P (operands[2]))
       {
 	emit_insn (gen_mulhisi3_internal2 (operands[0], operands[1], operands[2]));
 	DONE;
@@ -1150,8 +1150,8 @@
         && GET_MODE (XEXP (operands[1], 0)) != SImode)
       FAIL;
 
-    if ((GET_CODE (operands[2]) == CONST_INT
-	&& GET_CODE (operands[3]) == CONST_INT))
+    if ((CONST_INT_P (operands[2])
+	&& CONST_INT_P (operands[3])))
       {
 	int o2 = INTVAL (operands[2]);
 	int o3 = INTVAL (operands[3]);
@@ -1304,7 +1304,7 @@
   "(TARGET_V850E_UP)
    && ((INTVAL (operands[2]) ^ INTVAL (operands[3])) == 1)
    && ((INTVAL (operands[2]) + INTVAL (operands[3])) != 1)
-   && (GET_CODE (operands[5]) == CONST_INT
+   && (CONST_INT_P (operands[5])
       || REGNO (operands[0]) != REGNO (operands[5]))
    && REGNO (operands[0]) != REGNO (operands[4])"
   [(set (match_dup 0) (match_dup 6))
diff --git a/gcc/config/visium/visium.c b/gcc/config/visium/visium.c
index 431f64cfcad..48e02e04689 100644
--- a/gcc/config/visium/visium.c
+++ b/gcc/config/visium/visium.c
@@ -1902,7 +1902,7 @@ visium_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
 			   machine_mode mode)
 {
   if (GET_CODE (x) == PLUS
-      && GET_CODE (XEXP (x, 1)) == CONST_INT
+      && CONST_INT_P (XEXP (x, 1))
       && GET_CODE (XEXP (x, 0)) == REG && mode != BLKmode)
     {
       int offset = INTVAL (XEXP (x, 1));
@@ -1947,7 +1947,7 @@ visium_legitimize_reload_address (rtx x, machine_mode mode, int opnum,
 
   newrtx = tem ? tem : x;
   if (GET_CODE (newrtx) == PLUS
-      && GET_CODE (XEXP (newrtx, 1)) == CONST_INT
+      && CONST_INT_P (XEXP (newrtx, 1))
       && GET_CODE (XEXP (newrtx, 0)) == REG
       && BASE_REGISTER_P (REGNO (XEXP (newrtx, 0))))
     {
diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c
index 2b97fa2e270..802323c2f8e 100644
--- a/gcc/config/xtensa/xtensa.c
+++ b/gcc/config/xtensa/xtensa.c
@@ -534,9 +534,9 @@ smalloffset_mem_p (rtx op)
 	{
 	  rtx offset = XEXP (addr, 0);
 	  HOST_WIDE_INT val;
-	  if (GET_CODE (offset) != CONST_INT)
+	  if (!CONST_INT_P (offset))
 	    offset = XEXP (addr, 1);
-	  if (GET_CODE (offset) != CONST_INT)
+	  if (!CONST_INT_P (offset))
 	    return FALSE;
 
 	  val = INTVAL (offset);
@@ -723,7 +723,7 @@ gen_int_relational (enum rtx_code test_code, /* relational test (EQ, etc) */
     mode = GET_MODE (cmp1);
 
   /* Make sure we can handle any constants given to us.  */
-  if (GET_CODE (cmp1) == CONST_INT)
+  if (CONST_INT_P (cmp1))
     {
       HOST_WIDE_INT value = INTVAL (cmp1);
       unsigned HOST_WIDE_INT uvalue = (unsigned HOST_WIDE_INT)value;
@@ -748,13 +748,13 @@ gen_int_relational (enum rtx_code test_code, /* relational test (EQ, etc) */
     }
 
   /* See if we need to invert the result.  */
-  *p_invert = ((GET_CODE (cmp1) == CONST_INT)
+  *p_invert = ((CONST_INT_P (cmp1))
 	       ? p_info->invert_const
 	       : p_info->invert_reg);
 
   /* Comparison to constants, may involve adding 1 to change a LT into LE.
      Comparison between two registers, may involve switching operands.  */
-  if (GET_CODE (cmp1) == CONST_INT)
+  if (CONST_INT_P (cmp1))
     {
       if (p_info->const_add != 0)
 	cmp1 = GEN_INT (INTVAL (cmp1) + p_info->const_add);
@@ -1047,7 +1047,7 @@ xtensa_emit_move_sequence (rtx *operands, machine_mode mode)
   rtx src = operands[1];
 
   if (CONSTANT_P (src)
-      && (GET_CODE (src) != CONST_INT || ! xtensa_simm12b (INTVAL (src))))
+      && (!CONST_INT_P (src) || ! xtensa_simm12b (INTVAL (src))))
     {
       rtx dst = operands[0];
 
@@ -1283,7 +1283,7 @@ xtensa_expand_block_move (rtx *operands)
   rtx x;
 
   /* If this is not a fixed size move, just call memcpy.  */
-  if (!optimize || (GET_CODE (operands[2]) != CONST_INT))
+  if (!optimize || (!CONST_INT_P (operands[2])))
     return 0;
 
   bytes = INTVAL (operands[2]);
@@ -1810,7 +1810,7 @@ xtensa_emit_call (int callop, rtx *operands)
   static char result[64];
   rtx tgt = operands[callop];
 
-  if (GET_CODE (tgt) == CONST_INT)
+  if (CONST_INT_P (tgt))
     sprintf (result, "call%d\t" HOST_WIDE_INT_PRINT_HEX,
 	     WINDOW_SIZE, INTVAL (tgt));
   else if (register_operand (tgt, VOIDmode))
@@ -1977,7 +1977,7 @@ xtensa_legitimize_address (rtx x,
 
       /* Try to split up the offset to use an ADDMI instruction.  */
       if (GET_CODE (plus0) == REG
-	  && GET_CODE (plus1) == CONST_INT
+	  && CONST_INT_P (plus1)
 	  && !xtensa_mem_offset (INTVAL (plus1), mode)
 	  && !xtensa_simm8 (INTVAL (plus1))
 	  && xtensa_mem_offset (INTVAL (plus1) & 0xff, mode)
@@ -2400,7 +2400,7 @@ print_operand (FILE *file, rtx x, int letter)
       break;
 
     case 'K':
-      if (GET_CODE (x) == CONST_INT)
+      if (CONST_INT_P (x))
 	{
 	  int num_bits = 0;
 	  unsigned val = INTVAL (x);
@@ -2419,28 +2419,28 @@ print_operand (FILE *file, rtx x, int letter)
       break;
 
     case 'L':
-      if (GET_CODE (x) == CONST_INT)
+      if (CONST_INT_P (x))
 	fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INTVAL (x)) & 0x1f);
       else
 	output_operand_lossage ("invalid %%L value");
       break;
 
     case 'R':
-      if (GET_CODE (x) == CONST_INT)
+      if (CONST_INT_P (x))
 	fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x1f);
       else
 	output_operand_lossage ("invalid %%R value");
       break;
 
     case 'x':
-      if (GET_CODE (x) == CONST_INT)
+      if (CONST_INT_P (x))
 	printx (file, INTVAL (x));
       else
 	output_operand_lossage ("invalid %%x value");
       break;
 
     case 'd':
-      if (GET_CODE (x) == CONST_INT)
+      if (CONST_INT_P (x))
 	fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
       else
 	output_operand_lossage ("invalid %%d value");
@@ -2448,7 +2448,7 @@ print_operand (FILE *file, rtx x, int letter)
 
     case 't':
     case 'b':
-      if (GET_CODE (x) == CONST_INT)
+      if (CONST_INT_P (x))
 	{
 	  printx (file, INTVAL (x));
 	  fputs (letter == 't' ? "@h" : "@l", file);
@@ -2471,7 +2471,7 @@ print_operand (FILE *file, rtx x, int letter)
 	  if (GET_CODE (XEXP (x, 0)) != PLUS
 	      || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
 		  && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
-	      || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
+	      || !CONST_INT_P (XEXP (XEXP (x, 0), 1)))
 	    output_operand_lossage ("invalid %%t/%%b value");
 	  print_operand (file, XEXP (XEXP (x, 0), 0), 0);
 	  fputs (letter == 't' ? "@h" : "@l", file);
@@ -2505,7 +2505,7 @@ print_operand (FILE *file, rtx x, int letter)
 	fprintf (file, "%s", reg_names[xt_true_regnum (x)]);
       else if (GET_CODE (x) == MEM)
 	output_address (GET_MODE (x), XEXP (x, 0));
-      else if (GET_CODE (x) == CONST_INT)
+      else if (CONST_INT_P (x))
 	fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
       else
 	output_addr_const (file, x);
diff --git a/gcc/config/xtensa/xtensa.h b/gcc/config/xtensa/xtensa.h
index 70d948720e9..a9e6e7ded5d 100644
--- a/gcc/config/xtensa/xtensa.h
+++ b/gcc/config/xtensa/xtensa.h
@@ -625,7 +625,7 @@ typedef struct xtensa_args
    but rejecting CONST_DOUBLE.  */
 #define CONSTANT_ADDRESS_P(X)						\
   ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
-    || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH		\
+    || CONST_INT_P (X) || GET_CODE (X) == HIGH		\
     || (GET_CODE (X) == CONST)))
 
 /* A C expression that is nonzero if X is a legitimate immediate
diff --git a/gcc/cse.c b/gcc/cse.c
index 35840a6d5ca..5a6fcf8cbb7 100644
--- a/gcc/cse.c
+++ b/gcc/cse.c
@@ -1289,7 +1289,7 @@ find_reg_offset_for_const (struct table_elt *anchor_elt, HOST_WIDE_INT offs,
       if (REG_P (elt->exp)
 	  || (GET_CODE (elt->exp) == PLUS
 	      && REG_P (XEXP (elt->exp, 0))
-	      && GET_CODE (XEXP (elt->exp, 1)) == CONST_INT))
+	      && CONST_INT_P (XEXP (elt->exp, 1))))
 	{
 	  rtx x;
 
@@ -5029,7 +5029,7 @@ cse_insn (rtx_insn *insn)
       if (targetm.const_anchor
 	  && !src_related
 	  && src_const
-	  && GET_CODE (src_const) == CONST_INT)
+	  && CONST_INT_P (src_const))
 	{
 	  src_related = try_const_anchors (src_const, mode);
 	  src_related_is_const_anchor = src_related != NULL_RTX;
@@ -5998,7 +5998,7 @@ cse_insn (rtx_insn *insn)
 	if (targetm.const_anchor
 	    && REG_P (dest)
 	    && SCALAR_INT_MODE_P (GET_MODE (dest))
-	    && GET_CODE (sets[i].src_elt->exp) == CONST_INT)
+	    && CONST_INT_P (sets[i].src_elt->exp))
 	  insert_const_anchors (dest, sets[i].src_elt->exp, GET_MODE (dest));
 
 	elt->in_memory = (MEM_P (sets[i].inner_dest)
diff --git a/gcc/dwarf2out.c b/gcc/dwarf2out.c
index aa7fd7eb465..63cb01c8198 100644
--- a/gcc/dwarf2out.c
+++ b/gcc/dwarf2out.c
@@ -15129,7 +15129,7 @@ clz_loc_descriptor (rtx rtl, scalar_int_mode mode,
     msb = immed_wide_int_const
       (wi::set_bit_in_zero (GET_MODE_PRECISION (mode) - 1,
 			    GET_MODE_PRECISION (mode)), mode);
-  if (GET_CODE (msb) == CONST_INT && INTVAL (msb) < 0)
+  if (CONST_INT_P (msb) && INTVAL (msb) < 0)
     tmp = new_loc_descr (HOST_BITS_PER_WIDE_INT == 32
 			 ? DW_OP_const4u : HOST_BITS_PER_WIDE_INT == 64
 			 ? DW_OP_const8u : DW_OP_constu, INTVAL (msb), 0);
diff --git a/gcc/explow.c b/gcc/explow.c
index 7eb854bca4a..c74c689aead 100644
--- a/gcc/explow.c
+++ b/gcc/explow.c
@@ -2178,7 +2178,7 @@ anti_adjust_stack_and_probe (rtx size, bool adjust_back)
       if (temp != const0_rtx)
 	{
 	  /* Manual CSE if the difference is not known at compile-time.  */
-	  if (GET_CODE (temp) != CONST_INT)
+	  if (!CONST_INT_P (temp))
 	    temp = gen_rtx_MINUS (Pmode, size, rounded_size_op);
 	  anti_adjust_stack (temp);
 	  emit_stack_probe (stack_pointer_rtx);
diff --git a/gcc/expr.c b/gcc/expr.c
index 20e3f9ce337..d020627203b 100644
--- a/gcc/expr.c
+++ b/gcc/expr.c
@@ -1659,7 +1659,7 @@ rtx
 emit_block_move (rtx x, rtx y, rtx size, enum block_op_methods method)
 {
   unsigned HOST_WIDE_INT max, min = 0;
-  if (GET_CODE (size) == CONST_INT)
+  if (CONST_INT_P (size))
     min = max = UINTVAL (size);
   else
     max = GET_MODE_MASK (GET_MODE (size));
@@ -3052,7 +3052,7 @@ rtx
 clear_storage (rtx object, rtx size, enum block_op_methods method)
 {
   unsigned HOST_WIDE_INT max, min = 0;
-  if (GET_CODE (size) == CONST_INT)
+  if (CONST_INT_P (size))
     min = max = UINTVAL (size);
   else
     max = GET_MODE_MASK (GET_MODE (size));
diff --git a/gcc/genrecog.c b/gcc/genrecog.c
index f20089eeee8..82b00fde9ed 100644
--- a/gcc/genrecog.c
+++ b/gcc/genrecog.c
@@ -1687,7 +1687,7 @@ simplify_tests (state *s)
   for (decision *d = s->first; d; d = d->next)
     {
       uint64_t label;
-      /* Convert checks for GET_CODE (x) == CONST_INT and XWINT (x, 0) == N
+      /* Convert checks for CONST_INT_P (x) and XWINT (x, 0) == N
 	 into checks for const_int_rtx[N'], if N is suitably small.  */
       if (d->test.kind == rtx_test::CODE
 	  && d->if_statement_p (&label)
diff --git a/gcc/ree.c b/gcc/ree.c
index c63e1591ae3..03d610137f9 100644
--- a/gcc/ree.c
+++ b/gcc/ree.c
@@ -268,7 +268,7 @@ update_reg_equal_equiv_notes (rtx_insn *insn, machine_mode new_mode,
 	  rtx orig_src = XEXP (*loc, 0);
 	  /* Update equivalency constants.  Recall that RTL constants are
 	     sign-extended.  */
-	  if (GET_CODE (orig_src) == CONST_INT
+	  if (CONST_INT_P (orig_src)
 	      && HWI_COMPUTABLE_MODE_P (new_mode))
 	    {
 	      if (INTVAL (orig_src) >= 0 || code == SIGN_EXTEND)
@@ -336,7 +336,7 @@ combine_set_extension (ext_cand *cand, rtx_insn *curr_insn, rtx *orig_set)
 
   /* Merge constants by directly moving the constant into the register under
      some conditions.  Recall that RTL constants are sign-extended.  */
-  if (GET_CODE (orig_src) == CONST_INT
+  if (CONST_INT_P (orig_src)
       && HWI_COMPUTABLE_MODE_P (cand->mode))
     {
       if (INTVAL (orig_src) >= 0 || cand->code == SIGN_EXTEND)
diff --git a/gcc/reload1.c b/gcc/reload1.c
index 38ee356a791..2747f0b2e53 100644
--- a/gcc/reload1.c
+++ b/gcc/reload1.c
@@ -5994,7 +5994,7 @@ function_invariant_p (const_rtx x)
     return 1;
   if (GET_CODE (x) == PLUS
       && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
-      && GET_CODE (XEXP (x, 1)) == CONST_INT)
+      && CONST_INT_P (XEXP (x, 1)))
     return 1;
   return 0;
 }
diff --git a/gcc/tree-ssa-address.c b/gcc/tree-ssa-address.c
index 8004951d2e8..1d85e03ee2e 100644
--- a/gcc/tree-ssa-address.c
+++ b/gcc/tree-ssa-address.c
@@ -264,13 +264,13 @@ addr_for_mem_ref (struct mem_address *addr, addr_space_t as,
      into OFF and clear BSE.  Otherwise we may later try to pull a mode from
      BSE to generate a REG, which won't work with constants because they
      are modeless.  */
-  if (bse && GET_CODE (bse) == CONST_INT)
+  if (bse && CONST_INT_P (bse))
     {
       if (off)
 	off = simplify_gen_binary (PLUS, pointer_mode, bse, off);
       else
 	off = bse;
-      gcc_assert (GET_CODE (off) == CONST_INT);
+      gcc_assert (CONST_INT_P (off));
       bse = NULL_RTX;
     }
   gen_addr_rtx (pointer_mode, sym, bse, idx, st, off, &address, NULL, NULL);
diff --git a/gcc/var-tracking.c b/gcc/var-tracking.c
index 67f25c1c795..599c6bd7f33 100644
--- a/gcc/var-tracking.c
+++ b/gcc/var-tracking.c
@@ -2043,7 +2043,7 @@ vt_get_canonicalize_base (rtx loc)
 {
   while ((GET_CODE (loc) == PLUS
 	  || GET_CODE (loc) == AND)
-	 && GET_CODE (XEXP (loc, 1)) == CONST_INT
+	 && CONST_INT_P (XEXP (loc, 1))
 	 && (GET_CODE (loc) != AND
 	     || negative_power_of_two_p (INTVAL (XEXP (loc, 1)))))
     loc = XEXP (loc, 0);
@@ -2195,7 +2195,7 @@ vt_canonicalize_addr (dataflow_set *set, rtx oloc)
 	 canonicalize the base and we're done.  We'll normally have
 	 only one stack alignment anyway.  */
       if (GET_CODE (loc) == AND
-	  && GET_CODE (XEXP (loc, 1)) == CONST_INT
+	  && CONST_INT_P (XEXP (loc, 1))
 	  && negative_power_of_two_p (INTVAL (XEXP (loc, 1))))
 	{
 	  x = vt_canonicalize_addr (set, XEXP (loc, 0));
-- 
2.21.0


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