[PATCH V5, rs6000] Support vrotr<mode>3 for int vector types

["Kewen.Lin" <linkw at linux dot ibm dot com>]

Hi Segher,

Sorry for the late, I've addressed your comments in the attached patch.
Some points:
  1) Remove explict AND part.
  2) Rename predicate name to vint_reg_or_vint_const.
  3) Split test cases into altivec and power8.

As to the predicate name and usage, I checked the current vector shifts, 
they don't need to check const_vector specially (like right to left 
conversion), excepting for the one "vec_shr_<mode>", but it checks for
scalar const int.

Btw, I've changed the 
  +      rtx imm_vec = 
  +	simplify_const_unary_operation
back to 
  +      rtx imm_vec
  +	= simplify_const_unary_operation
Otherwise check_GNU_style will report "Trailing operator" error.  :(

Bootstrapped and regtested on powerpc64le-unknown-linux-gnu.

Thanks,
Kewen

------------

gcc/ChangeLog

2019-08-02  Kewen Lin  <linkw@gcc.gnu.org>

	* config/rs6000/predicates.md (vint_reg_or_vint_const): New predicate.
	* config/rs6000/vector.md (vrotr<mode>3): New define_expand.

gcc/testsuite/ChangeLog

2019-08-02  Kewen Lin  <linkw@gcc.gnu.org>

	* gcc.target/powerpc/vec_rotate-1.c: New test.
	* gcc.target/powerpc/vec_rotate-2.c: New test.
	* gcc.target/powerpc/vec_rotate-3.c: New test.
	* gcc.target/powerpc/vec_rotate-4.c: New test.

Attachment: expand_v5.diff
Description: Text document