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[PATCH], PowerPC #14, Add pc-relative support to load up addresses

This is patch #14, and it adds support to load up addresses with pc-relative
addressing.  Note, a later patch will add support for actually using the
pc-relative support directly.  In theory with patches 11-14 applied, you could
use -mpcrel.  However, for now, -mpcrel will not be enabled by default.

I have checked this by doing a boostrap on a little endian power8 system, and
there were no regressions in the test suite.  Can I check this into the FSF?

This is a series of separate patches to add functionality to the PowerPC
backend to support future processors.  Here is a high level summary of the

 * Patches 1-8, have already been applied
 * Patch 9 has been rewritten in patches 12-13
 * Patch 10 is withdrawn for now
 * Patch 11 adds DS offset mode to rs6000.c's reg_addr
 * Patch 12 adds a new enumeration for instruction format
 * Patch 13 adds support for matching prefixed insns
 * Patch 14 adds pc-relative support to load up addresses
 * Patch 15 renamed some functions to be smaller
 * Patch 16 updated a comment and moved a predicate
 * Patch 17 adds the prefixed RTL attribute & emitting 'p' before prefixed
 * Patch 18 adds prefixed support for scalar types
 * Patch 19 uses a separate 'future' cost structure
 * Patch 20 clones for initial scheduling on

The following patches have not yet been written, but I expect them to be:

 * Patch 21 finish prefixed insn support for vectors & 128-bit int/floats
 * Patch 22 enable pc-relative by default
 * Patch 23 add pcrel linker optimization
 * Patch 24 new tests

2019-07-24  Michael Meissner  <>

	* config/rs6000/rs6000.c (rs6000_emit_move): Add support to load
	up addresses if we have pc-relative support.
	* config/rs6000/ (pcrel_addr): New insn.
	(pcrel_ext_addr): New insn.

Index: gcc/config/rs6000/rs6000.c
--- gcc/config/rs6000/rs6000.c	(revision 273778)
+++ gcc/config/rs6000/rs6000.c	(working copy)
@@ -9779,6 +9779,20 @@ rs6000_emit_move (rtx dest, rtx source,
+      /* Handle pc-relative addresses, either external symbols or internal
+	 within the function.  */
+      if (TARGET_PCREL)
+	{
+	  const unsigned addr_flags = (ADDR_VALIDATE_PCREL_LOCAL
+	  if (addr_validate_p (operands[1], INSN_FORM_PREFIXED, addr_flags))
+	    {
+	      emit_insn (gen_rtx_SET (operands[0], operands[1]));
+	      return;
+	    }
+	}
       if (DEFAULT_ABI == ABI_V4
 	  && mode == Pmode && mode == SImode
 	  && flag_pic == 1 && got_operand (operands[1], mode))
Index: gcc/config/rs6000/
--- gcc/config/rs6000/	(revision 273777)
+++ gcc/config/rs6000/	(working copy)
@@ -9885,6 +9885,26 @@ (define_expand "restore_stack_nonlocal"
   operands[6] = gen_rtx_PARALLEL (VOIDmode, p);
+;; Load up a pc-relative address.  The length is 12 because the assembler may
+;; need to add a NOP to align the PADDI so it doesn't cross a 32-btye boundary.
+(define_insn "*pcrel_addr"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
+	(match_operand:DI 1 "pcrel_address"))]
+  "pla %0,%a1"
+  [(set_attr "length" "12")])
+;; Load up a pc-relative address to an external symbol.  If the symbol and the
+;; program are both defined in the main program, the linker will optimize this
+;; to a PADDI.  Otherwise, it will create a GOT address that is relocated by
+;; the dynamic linker and loaded up.
+(define_insn "*pcrel_ext_addr"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
+	(match_operand:DI 1 "pcrel_external_address"))]
+  "pld %0,%a1"
+  [(set_attr "length" "12")])
 ;; TOC register handling.
 ;; Code to initialize the TOC register...

Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email:, phone: +1 (978) 899-4797

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