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[patch1/2][arm][PR90317]: fix sha1 patterns


Greetings,

This patch fixes:

1) Ice message thrown when using the crypto_sha1h intrinsic due to
incompatible mode used for zero_extend. Removed zero extend as it is
not a good choice for vector modes and using an equivalent single
mode like TI (128bits) instead of V4SI produces extra instructions
making it inefficient.

This affects gcc version 8 and above.

2) Incorrect combine optimizations made due to vec_select usage
in the sha1 patterns on arm. The patterns should only combine
a vec select within a sha1h<op> instruction when the lane is 0.

This affects gcc version 5 and above.

- Fixed by explicitly declaring the valid const int for such
optimizations. For cases when the lane is not 0, the vector
lane selection now occurs in a e.g. vmov instruction prior 
to sha1h<op>.

- Updated the sha1h testcases on arm to check for additional
cases with custom vector lane selection.

The intrinsic functions for the sha1 patterns have also been
simplified which seems to eliminate extra vmovs like:
- vmov.i32 q8, #0.

Bootstrapped and tested on arm-none-linux-gnueabihf.

Cheers,
Syl

gcc/ChangeLog:

2019-07-03  Sylvia Taylor  <sylvia.taylor@arm.com>

	PR target/90317
	* config/arm/arm_neon.h
	(vsha1h_u32): Refactor.
	(vsha1cq_u32): Likewise.
	(vsha1pq_u32): Likewise.
	(vsha1mq_u32): Likewise.
	* config/arm/crypto.md:
	(crypto_sha1h): Remove zero extend, correct vec select.
	(crypto_sha1c): Correct vec select.
	(crypto_sha1m): Likewise.
	(crypto_sha1p): Likewise.

gcc/testsuite/ChangeLog:

2019-07-03  Sylvia Taylor  <sylvia.taylor@arm.com>

	PR target/90317
	* gcc.target/arm/crypto-vsha1cq_u32.c (foo): Change.
	(GET_LANE, TEST_SHA1C_VEC_SELECT): New.
	* gcc.target/arm/crypto-vsha1h_u32.c (foo): Change.
	(GET_LANE, TEST_SHA1H_VEC_SELECT): New.
	* gcc.target/arm/crypto-vsha1mq_u32.c (foo): Change.
	(GET_LANE, TEST_SHA1M_VEC_SELECT): New.
	* gcc.target/arm/crypto-vsha1pq_u32.c (foo): Change.
	(GET_LANE, TEST_SHA1P_VEC_SELECT): New.

Attachment: diff.txt
Description: diff.txt


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