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Re: [PATCH] Prepare for prefixed instructions on PowerPC
- From: Michael Meissner <meissner at linux dot ibm dot com>
- To: Segher Boessenkool <segher at kernel dot crashing dot org>
- Cc: Michael Meissner <meissner at linux dot ibm dot com>, gcc-patches at gcc dot gnu dot org, dje dot gcc at gmail dot com
- Date: Tue, 2 Jul 2019 19:36:21 -0400
- Subject: Re: [PATCH] Prepare for prefixed instructions on PowerPC
- References: <20190627201800.GA30249@ibm-toto.the-meissners.org> <20190701212704.GF18316@gate.crashing.org>
On Mon, Jul 01, 2019 at 04:27:05PM -0500, Segher Boessenkool wrote:
> The entry before the 8 is split as well. Maybe that should be "4", to
> stand out? I don't know what works better; your choice.
I'll look into it. Note, the length is used in two places. One at the end to
generate the appropriate branches, but the other is in rs6000_insn_cost inside
rs6000.c. This occurs before the final passes, so it is important that even
though the insn will be split, that the length is still set. However, things
are rather inconsistant, in that sometimes the length field is accurate, and
sometimes not.
I'm finding that the rs6000_insn_cost issue really muddies things up,
particularly if a vector load/store insn is done in gpr registers, where it can
be 4 insns.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797