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[PATCH 5/6] rs6000: wl -> d+p6
2019-05-21 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/constraints.md (define_register_constraint "wl"):
Delete.
* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
RS6000_CONSTRAINT_wl.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
(rs6000_init_hard_regno_mode_ok): Adjust.
* config/rs6000/rs6000.md: Replace "wl" constraint by "d" with "p6".
* doc/md.texi (Machine Constraints): Adjust.
---
gcc/config/rs6000/constraints.md | 3 ---
gcc/config/rs6000/rs6000.c | 6 ------
gcc/config/rs6000/rs6000.h | 1 -
gcc/config/rs6000/rs6000.md | 4 ++--
gcc/doc/md.texi | 5 +----
5 files changed, 3 insertions(+), 16 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 90a94c1..802ce44 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -74,9 +74,6 @@ (define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]"
(define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]"
"FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.")
-(define_register_constraint "wl" "rs6000_constraints[RS6000_CONSTRAINT_wl]"
- "Floating point register if the LFIWAX instruction is enabled or NO_REGS.")
-
;; NO_REGs register constraint, used to merge mov{sd,sf}, since movsd can use
;; direct move directly, and movsf can't to move between the register sets.
;; There is a mode_attr that resolves to wa for SDmode and wn for SFmode
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index d6ffc36..6124bce 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -2513,7 +2513,6 @@ rs6000_debug_reg_global (void)
"wf reg_class = %s\n"
"wg reg_class = %s\n"
"wi reg_class = %s\n"
- "wl reg_class = %s\n"
"wp reg_class = %s\n"
"wq reg_class = %s\n"
"wr reg_class = %s\n"
@@ -2534,7 +2533,6 @@ rs6000_debug_reg_global (void)
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]],
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
@@ -3156,7 +3154,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
wf - Preferred register class for V4SFmode.
wg - Float register for power6x move insns.
wi - FP or VSX register to hold 64-bit integers for VSX insns.
- wl - Float register if we can do 32-bit signed int loads.
wn - always NO_REGS.
wr - GPR if 64-bit mode is permitted.
ws - Register class to do ISA 2.06 DF operations.
@@ -3191,9 +3188,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
if (TARGET_MFPGPR) /* DFmode */
rs6000_constraints[RS6000_CONSTRAINT_wg] = FLOAT_REGS;
- if (TARGET_LFIWAX)
- rs6000_constraints[RS6000_CONSTRAINT_wl] = FLOAT_REGS; /* DImode */
-
if (TARGET_POWERPC64)
{
rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS;
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 27055a6..176f34d 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1254,7 +1254,6 @@ enum r6000_reg_class_enum {
RS6000_CONSTRAINT_wf, /* VSX register for V4SF */
RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */
RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */
- RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */
RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */
RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */
RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 33a6de7..454518e 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -1019,7 +1019,7 @@ (define_insn_and_split "*extendhi<mode>2_dot2"
(define_insn "extendsi<mode>2"
[(set (match_operand:EXTSI 0 "gpc_reg_operand"
- "=r, r, wl, wa, wi, v, v, wr")
+ "=r, r, d, wa, wi, v, v, wr")
(sign_extend:EXTSI (match_operand:SI 1 "lwa_operand"
"YZ, r, Z, Z, r, v, v, ?wa")))]
""
@@ -1035,7 +1035,7 @@ (define_insn "extendsi<mode>2"
[(set_attr "type" "load,exts,fpload,fpload,mffgpr,vecexts,vecperm,mftgpr")
(set_attr "sign_extend" "yes")
(set_attr "length" "4,4,4,4,4,4,8,8")
- (set_attr "isa" "*,*,*,p8v,p8v,p9v,p8v,p8v")])
+ (set_attr "isa" "*,*,p6,p8v,p8v,p9v,p8v,p8v")])
(define_split
[(set (match_operand:EXTSI 0 "int_reg_operand")
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 7ec1740..2d531cc 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3198,7 +3198,7 @@ Any VSX register if the @option{-mvsx} option was used or NO_REGS.
When using any of the register constraints (@code{wa}, @code{wd},
@code{wf}, @code{wg}, @code{wi},
-@code{wl}, @code{wp}, @code{wq}, @code{ws},
+@code{wp}, @code{wq}, @code{ws},
@code{wt}, @code{wv}, or @code{ww})
that take VSX registers, you must use @code{%x<n>} in the template so
that the correct register is used. Otherwise the register number
@@ -3262,9 +3262,6 @@ If @option{-mmfpgpr} was used, a floating point register or NO_REGS.
@item wi
FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.
-@item wl
-Floating point register if the LFIWAX instruction is enabled or NO_REGS.
-
@item wn
No register (NO_REGS).
--
1.8.3.1