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[PATCH 16/46] i386: Emulate MMX pshufw with SSE
- From: "H.J. Lu" <hjl dot tools at gmail dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: Uros Bizjak <ubizjak at gmail dot com>
- Date: Fri, 1 Feb 2019 13:17:39 -0800
- Subject: [PATCH 16/46] i386: Emulate MMX pshufw with SSE
- References: <20190201211809.963-1-hjl.tools@gmail.com>
Emulate MMX pshufw with SSE. Only SSE register source operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_pshufw_1): Check TARGET_MMX_WITH_SSE
for SSE emulation.
(*vec_dupv4hi): Add SSE emulation.
---
gcc/config/i386/mmx.md | 25 +++++++++++++++----------
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 74efe680d9e..599c762e166 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -1344,9 +1344,9 @@
})
(define_insn "mmx_pshufw_1"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
+ [(set (match_operand:V4HI 0 "register_operand" "=y,Yy")
(vec_select:V4HI
- (match_operand:V4HI 1 "nonimmediate_operand" "ym")
+ (match_operand:V4HI 1 "nonimmediate_operand" "ym,Yy")
(parallel [(match_operand 2 "const_0_to_3_operand")
(match_operand 3 "const_0_to_3_operand")
(match_operand 4 "const_0_to_3_operand")
@@ -1360,11 +1360,14 @@
mask |= INTVAL (operands[5]) << 6;
operands[2] = GEN_INT (mask);
- return "pshufw\t{%2, %1, %0|%0, %1, %2}";
+ if (TARGET_MMX_WITH_SSE)
+ return "%vpshuflw\t{%2, %1, %0|%0, %1, %2}";
+ else
+ return "pshufw\t{%2, %1, %0|%0, %1, %2}";
}
- [(set_attr "type" "mmxcvt")
+ [(set_attr "type" "mmxcvt,sselog")
(set_attr "length_immediate" "1")
- (set_attr "mode" "DI")])
+ (set_attr "mode" "DI,TI")])
(define_insn "mmx_pswapdv2si2"
[(set (match_operand:V2SI 0 "register_operand" "=y")
@@ -1378,15 +1381,17 @@
(set_attr "mode" "DI")])
(define_insn "*vec_dupv4hi"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
+ [(set (match_operand:V4HI 0 "register_operand" "=y,Yy")
(vec_duplicate:V4HI
(truncate:HI
- (match_operand:SI 1 "register_operand" "0"))))]
+ (match_operand:SI 1 "register_operand" "0,Yy"))))]
"TARGET_SSE || TARGET_3DNOW_A"
- "pshufw\t{$0, %0, %0|%0, %0, 0}"
- [(set_attr "type" "mmxcvt")
+ "@
+ pshufw\t{$0, %0, %0|%0, %0, 0}
+ %vpshuflw\t{$0, %1, %0|%0, %1, 0}"
+ [(set_attr "type" "mmxcvt,ssemov")
(set_attr "length_immediate" "1")
- (set_attr "mode" "DI")])
+ (set_attr "mode" "DI,TI")])
(define_insn_and_split "*vec_dupv2si"
[(set (match_operand:V2SI 0 "register_operand" "=y,Yx,Yy")
--
2.20.1