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Re: [PATCH] [MIPS] GCC: Fix Loongson3 LLSC Errata


Paul Hua <paul.hua.gm@gmail.com> 于2018年11月30日周五 下午8:46写道:
>
> In some older Loongson3 processors there is a LL/SC errata that can
> cause the CPU to deadlock occasionally.  The details are very
> complicated. We find a way to work around this errata by a) adding a
> sync before ll/lld instruction, b) adding a sync
> before branch target that between ll and sc. The assembler do the jobs
> 'a', gcc do the jobs 'b'.

Since it is not only about gcc, and also about as,
I guess we should check whether as support the new added option,
if so, we can call it with that option.

>
> This patch also add a configure options
> --with-mips-fix-loongson3-llsc=[yes|no] to enable fix-loongson3-llsc
> by config.

Should we add a predefined macro?
some manully writen asm code need some adjustment, such as linux kernel.

It need adjustment the label address if a `sync' is inserted.

https://patchwork.linux-mips.org/patch/21134/

- "1: "user_ll("%1", "%4")" # __futex_atomic_op\n" \
+ "1: # __futex_atomic_op\n" \
+ __WAR_LLSC_MB \
+ " "user_ll("%1", "%4")" \n" \
  " .set pop \n" \
  " " insn " \n" \
  " .set "MIPS_ISA_ARCH_LEVEL" \n" \
@@ -70,8 +72,9 @@
  " j 3b \n" \
  " .previous \n" \
  " .section __ex_table,\"a\" \n" \
- " "__UA_ADDR "\t1b, 4b \n" \
- " "__UA_ADDR "\t2b, 4b \n" \
+ " "__UA_ADDR "\t(1b + 0), 4b \n" \
+ " "__UA_ADDR "\t(1b + 4), 4b \n" \
+ " "__UA_ADDR "\t(2b + 0), 4b \n" \


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