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Re: [PATCH] combine: Do not combine moves from hard registers
- From: Segher Boessenkool <segher at kernel dot crashing dot org>
- To: Sam Tebbs <Sam dot Tebbs at arm dot com>
- Cc: Steve Ellcey <sellcey at cavium dot com>, Andreas Schwab <schwab at suse dot de>, "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>, "bergner at linux dot ibm dot com" <bergner at linux dot ibm dot com>
- Date: Mon, 12 Nov 2018 06:53:39 -0600
- Subject: Re: [PATCH] combine: Do not combine moves from hard registers
- References: <mvmbm7jr5nm.fsf@suse.de> <1540571945.12895.67.camel@cavium.com> <20181026164805.GN5205@gate.crashing.org> <7bc8697f-a09e-627f-b032-eba5ecb682ac@arm.com> <20181108203418.GT5994@gate.crashing.org> <e9104024-2f6a-6cb8-e366-39b96f7a72f2@arm.com>
On Mon, Nov 12, 2018 at 11:54:37AM +0000, Sam Tebbs wrote:
> On 11/08/2018 08:34 PM, Segher Boessenkool wrote:
>
> > On Thu, Nov 08, 2018 at 03:44:44PM +0000, Sam Tebbs wrote:
> >> Does your patch fix the incorrect generation of "scvtf s1, s1"? I was
> >> looking at the issue as well and don't want to do any overlapping work.
> > I don't know. Well, there are no incorrect code issues I know of at all
> > now; but you mean that it is taking an instruction more than you would
> > like to see, I suppose?
>
> Yes, I am referring to the extra instruction being generated. In my
> opinion is incorrect code generation since the intention is that it
> shouldn't be generated, and shouldn't based on the relevant code and
> patterns implemented.
That is not what incorrect code means; it is a "missed optimisation",
instead.
Anyway, does it now do what you want?
(PR87763 btw)
Segher