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Re: [PATCH][AArch64] Support zero-extended move to FP register

From: Richard Henderson <rth at twiddle dot net>
To: Wilco Dijkstra <Wilco dot Dijkstra at arm dot com>, Richard Earnshaw <Richard dot Earnshaw at arm dot com>, GCC Patches <gcc-patches at gcc dot gnu dot org>
Cc: nd <nd at arm dot com>
Date: Fri, 28 Sep 2018 09:45:43 -0700
Subject: Re: [PATCH][AArch64] Support zero-extended move to FP register
References: <DB5PR08MB1030659B194FE4FEE11AB4A083140@DB5PR08MB1030.eurprd08.prod.outlook.com> <dbb31749-26a5-18a3-3d0d-e87aed3be15c@arm.com> <DB5PR08MB1030130B633124B391C29E3483EC0@DB5PR08MB1030.eurprd08.prod.outlook.com>

On 9/28/18 9:29 AM, Wilco Dijkstra wrote:
> +  [(set (match_operand:DI 0 "register_operand" "=r,r,w,w")
> +        (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,r,m")))]
>    ""
>    "@
>     uxtw\t%0, %w1
> -   ldr\t%w0, %1"
> -  [(set_attr "type" "extend,load_4")]
> +   ldr\t%w0, %1
> +   fmov\t%s0, %w1

If you're going to add moves r->w, why not also go ahead and add w->r.
There are also HImode fmov zero-extensions, fwiw.


r~

Follow-Ups:
- Re: [PATCH][AArch64] Support zero-extended move to FP register
  - From: Wilco Dijkstra

References:
- [PATCH][AArch64] Support zero-extended move to FP register
  - From: Wilco Dijkstra
- Re: [PATCH][AArch64] Support zero-extended move to FP register
  - From: Richard Earnshaw (lists)
- Re: [PATCH][AArch64] Support zero-extended move to FP register
  - From: Wilco Dijkstra

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